IP Library › Granted Patent US 11,342,916
Granted Patent B2
US 11,342,916 · App. 16/883,753 · Granted May 24, 2022

Schottky-CMOS asynchronous logic cells

Inventors: Augustine Wei-Chun Chang (Mountain View, CA); Pierre Dermy (Reno, NV)
Assignee: SCHOTTKY LSI, INC.
H03K19/0956H01L25/065H01L27/0207H01L27/105H01L27/10897H01L27/112H01L27/11253H01L27/11286H01L27/11293H01L27/11526H01L27/11546H01L27/11807H01L28/00H01L31/032H01L31/0376H01L31/072H01L31/074H03K19/01707H03K19/0948H03K19/17728H01L28/20H01L2924/0002Y02E10/50
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Quick Facts
Patent No.
US 11,342,916
App. No.
16/883,753
Granted
May 24, 2022
Kind
B2
Abstract

Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

Claims (26)

1. An integrated circuit implementing a Schottky-CMOS multiplexer (MUX) gate system, the integrated circuit comprising:

a first input coupled to a cathode of a first Schottky diode and a gate node of a first N-type transistor;

x additional inputs coupled to x respective cathodes of a first set of Schottky diodes and x respective gate nodes of x additional N-type transistors, wherein x is an integer number;

an output of the first Schottky diode is coupled to an anode of a second Schottky diode and a gate node of a first P-type transistor;

x outputs of the first set of Schottky diodes coupled to x respective anodes of a second set of Schottky diodes and x respective gate nodes of x additional P-type transistors;

an output of the second Schottky diode is coupled to respective gate nodes of a second N-type transistor and a second P-type transistor; and

x outputs of the second set of Schottky diodes coupled to the respective gate nodes of the second N-type transistor and the second P-type transistor, the output of the second N-type transistor and the second P-type transistor is coupled to an output of the MUX gate system.

2. The integrated circuit of claim 1 , wherein the second P-type transistor and the second n-type transistor are a CMOS inverter.

3. The integrated circuit of claim 2 , wherein the CMOS inverter is biased between a high voltage supply and a low voltage supply.

4. The integrated circuit of claim 1 , wherein a threshold forward voltage of the second Schottky diode is less than a threshold voltage of the second N-type transistor.

5. The integrated circuit of claim 1 , wherein a threshold forward voltage of the second Schottky diode is less than a threshold voltage of the second P-type transistor.

6. The integrated circuit of claim 1 , wherein respective threshold forward voltages of the first Schottky diode and the first set of Schottky diodes are less than respective threshold voltages of the first N-type transistor and x additional N-type transistors.

7. The integrated circuit of claim 1 , wherein respective threshold forward voltages of the second Schottky diode and the second set of Schottky diodes are less than respective threshold voltages of the first P-type transistor and x additional P-type transistors.

8. The integrated circuit of claim 1 , further comprising:

a third N-type transistor including:

a third N-type transistor input coupled to the output of the second N-type transistor, and

a third N-type transistor output coupled to an input of the second N-type transistor; and

a third P-type transistor including:

a third P-type transistor input coupled to the output of the second P-type transistor, and

a third P-type transistor output coupled to an input of the second P-type transistor.

9. The integrated circuit of claim 8 , wherein the third N-type transistor and the third P-type transistor operate as feedback logic.

10. The integrated circuit of claim 1 , wherein the first N-type transistor is coupled to a plurality of first N-type transistors in series.

11. The integrated circuit of claim 1 , wherein the first Schottky diode is coupled to a plurality of first Schottky diode in parallel.

12. The integrated circuit of claim 1 , wherein the integrated circuit is configured for asynchronous operation.

13. The integrated circuit of claim 1 , wherein x is greater than or equal to 3.

14. The integrated circuit of claim 1 , wherein the first Schottky diode is a P-type Schottky diode and the second Schottky diode is an N-type Schottky diode.

Continuity (9)
Continuation 15817026 · Nov 17, 2017
Continuation 15484040 · Apr 10, 2017
Continuation In Part 15358049 · Nov 21, 2016
Continuation In Part PCTUS2015055020 · Oct 9, 2015
Continuation 14793690 · Jul 7, 2015
Continuation 13931315 · Jun 28, 2013
Division 12343465 · Dec 23, 2008
Provisional Application 62062800 · Oct 10, 2014
Related Publication 20200287546A1 · Sep 10, 2020
Cited By (2)
US 12,520,572 US 12,574,033