Schottky-CMOS static random-access memory
Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output is coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.
1 . A static random access memory (SRAM) array, comprising:
a substrate; and
a plurality of bit cells formed on the substrate, wherein at least one of the plurality of bit cells further including:
a latch formed from two cross-coupled inverters, the two cross-coupled inverters including a first inverter and a second inverter that are driven between a word line write signal and a word line read signal, wherein an input of the first inverter is cross-coupled to an output of the second inverter, and an output of the first inverter is cross-coupled to an input of the second inverter; and
a first Schottky barrier diode (SBD) and a second SBD, wherein the first SBD are electrically coupled between the output of the first inverter and a first bit signal, and the second SBD are electrically coupled between the output of the second inverter and a second bit signal, the first and second bit signals being complementary signals, wherein each of the first and second inverters includes two complementary metal oxide semiconductor (CMOS) transistors, and the first SBD is integrated in a substantially shallow diffusion bed associated with a drain of a first CMOS transistor of the first and second inverters.
2 . The SRAM array of claim 1 , wherein the first SBD and the first CMOS transistor are electrically coupled to each other via a buried contact.
3 . The SRAM array of claim 1 , wherein the first and second SBDs include a respective low threshold SBD having a barrier voltage drop substantially less than 0.5V.
4 . The SRAM array of claim 1 , wherein the first and second SBDs include a respective low threshold SBD further including a barrier metal, a doped semiconductor well and a silicide layer.
5 . The SRAM array of claim 4 , wherein the doped semiconductor well is formed in an epitaxial layer on the substrate and isolated by a doped isolation ring.
6 . The SRAM array of claim 4 , wherein the barrier metal includes one or more of molybdenum, platinum, chromium, tungsten, and silicides thereof.
7 . The SRAM array of claim 1 , wherein the second SBD is integrated in an extended area of a transistor drain bed of a second CMOS transistor of the first and second inverters.
8 . The SRAM array of claim 1 , wherein the first SBD further includes a doped semiconductor well and a silicide layer, and the doped semiconductor well is integrated in the substantially shallow drain diffusion bed associated with the drain of the first CMOS transistor of the first and second inverters, and wherein the at least one of the plurality of bit cells includes a terminal to electrically access both the doped
semiconductor well and the drain of the first CMOS transistor of the first and second inverters.
9 . The SRAM array of claim 1 , wherein the two cross-coupled inverters includes one or more non-planar transistors.
10 . The SRAM array of claim 9 , wherein the non-planar transistor includes a Fin-type field effect transistor (FinFET), and a gate of the FinFET further includes one or more fins.
11 . The SRAM array of claim 1 , wherein the substrate includes a silicon-on-insulator substrate.
12 . The SRAM array of claim 11 , wherein the silicon-on-insulator substrate includes a plurality of faceted S/D islands that contains the first and second SBDs.
13 . The SRAM array of claim 1 , further comprising:
readout circuit coupled to receive the first and second bit signals, wherein the readout circuit further includes:
a sense amplifier configured to amplify the first and second bit signals; and a readout latch coupled to the sense amplifier and configured to hold the amplifier bit signals.
14 . The SRAM array of claim 13 , wherein the sense amplifier is configured to receive the first and second bit signals via a first set of low threshold SBDs.
15 . The SRAM array of claim 13 , wherein the sense amplifier and the readout latch are electrically coupled to each other via a second set of low threshold SBDs.
16 . The SRAM array of claim 1 , further comprising:
write circuit configured to receive input data and write the input data to the at least one of the plurality of bit cells.
17 . The SRAM array of claim 16 , wherein the write circuit further includes a SBD pair that is electrically coupled at an output of the write circuit and configured to isolate capacitor loading at the output.
18 . The SRAM array of claim 1 , wherein the first inverter includes two complementary transistors having variable threshold voltages.
19 . The SRAM array of claim 1 , wherein each of the CMOS transistors of the first and second inverters has a respective preferred size determined according to a minimum feature size that could be accomplished by a corresponding transistor technology used to manufacture the complementary transistors.
20 . The SRAM array of claim 1 , wherein the first and second SBDs have a respective preferred size determined according to a minimum feature size of a corresponding Schottky barrier diode technology.