Schottky-CMOS asynchronous logic cells
Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.
1. An integrated circuit implementing a Schottky-CMOS multiplexer (MUX) gate system, the integrated circuit comprising:
a plurality of inputs coupled with a first stage of the integrated circuit, the first stage including a plurality of first Schottky diodes and a plurality of N-type transistors, wherein each input is coupled with a respective first Schottky diode and a respective N-type transistor;
a plurality of outputs of the first stage of the integrated circuit coupled with a second stage of the integrated circuit, the second stage including a plurality of second Schottky diodes and a plurality of P-type transistors, wherein each output is coupled with a respective second Schottky diode and a respective P-type transistor;
a plurality of outputs of the second stage of the integrated circuit coupled with a set of transistors including a P-type transistor and an N-type transistor; and
an output of the set of transistors coupled with an output of the MUX gate system.
2. The integrated circuit of claim 1 , wherein the set of transistors is a CMOS inverter.
3. The integrated circuit of claim 2 , wherein the CMOS inverter is biased between a high voltage supply and a low voltage supply.
4. The integrated circuit of claim 1 , wherein a threshold forward voltage of the plurality of second Schottky diodes is less than a threshold voltage of the N-type transistor of the set of transistors.
5. The integrated circuit of claim 1 , wherein a threshold forward voltage of the plurality of second Schottky diodes is less than a threshold voltage of the P-type transistor of the set of transistors.
6. The integrated circuit of claim 1 , wherein respective threshold forward voltages of the plurality of first Schottky diodes are less than respective threshold voltages of the plurality of N-type transistors.
7. The integrated circuit of claim 1 , wherein respective threshold forward voltages of the plurality of second Schottky diodes are less than respective threshold voltages of the plurality of P-type transistors.
8. The integrated circuit of claim 1 , wherein the set of transistors is a first set of transistors, and the integrated circuit further comprises:
a second set of transistors including an N-type transistor and a P-type transistor, where the second set of transistors is coupled with an input and an output of the first set of transistors.
9. The integrated circuit of claim 8 , wherein the second set of transistors operates as feedback logic.
10. The integrated circuit of claim 1 , wherein an N-type transistor coupled with a respective input is further coupled with a subset of N-type transistors in series.
11. The integrated circuit of claim 1 , wherein a first Schottky diode coupled with a respective input is further coupled with a subset of first Schottky diodes in parallel.
12. The integrated circuit of claim 1 , wherein the integrated circuit is configured for asynchronous operation.
13. The integrated circuit of claim 1 , wherein the plurality of inputs includes at least four inputs.
14. The integrated circuit of claim 1 , wherein the plurality of first Schottky diodes is a plurality of P-type Schottky diodes and the plurality of second Schottky diodes is a plurality of N-type Schottky diodes.
15. The integrated circuit of claim 1 , wherein each input is coupled with a respective cathode of the first Schottky diode and a respective gate node of the N-type transistor.
16. The integrated circuit of claim 1 , wherein each output of the plurality of outputs of the first stage is coupled with a respective anode of the second Schottky diode and a respective gate node of the P-type transistor.
17. The integrated circuit of claim 1 , wherein the plurality of outputs of the second stage are coupled with a respective gate node of the N-type transistor of the set of transistors and a respective gate node of the P-type transistor of the set of transistors.