Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same

1. A three-dimensional memory device, comprising:

a substrate comprising a III-V compound substrate semiconductor layer;

an alternating stack of insulating layers and electrically conductive layers located over the III-V compound substrate semiconductor layer;

a memory opening vertically extending through the alternating stack; and

a memory opening fill structure located in the memory opening and comprising a III-V compound semiconductor pedestal in contact with the III-V compound substrate semiconductor layer, a vertical semiconductor channel, and a memory film located adjacent to the vertical semiconductor channel;

wherein the substrate comprises:

a single crystalline silicon layer; and

a germanium-containing buffer layer located on top of the single crystalline silicon layer, wherein the III-V compound substrate semiconductor layer is located over the germanium-containing buffer layer.

2. The three-dimensional memory device of claim 1 , wherein:

the germanium-containing buffer layer is epitaxially aligned to the single crystalline silicon layer; and

the III-V compound substrate semiconductor layer is epitaxially aligned to the germanium-containing buffer layer.

3. The three-dimensional memory device of claim 1 , wherein:

the III-V compound substrate semiconductor layer is single crystalline; and

the III-V compound semiconductor pedestal is epitaxially aligned to the III-V compound substrate semiconductor layer.

4. The three-dimensional memory device of claim 3 , wherein the vertical semiconductor channel comprises a III-V compound semiconductor channel material.

5. The three-dimensional memory device of claim 4 , further comprising a drain region located at an upper end of the vertical semiconductor channel, wherein:

the III-V compound semiconductor pedestal and the III-V compound substrate semiconductor layer have a doping of a first conductivity type; and

the drain region has a doping of a second conductivity type that is an opposite of the first conductivity type.

6. The three-dimensional memory device of claim 5 , wherein:

the III-V compound semiconductor channel material comprises polycrystalline gallium arsenide or indium gallium arsenide; and

the drain region comprises a graded III-V compound semiconductor material having a compositional gradient that provides a variable band gap that decreases with a distance from an interface with the vertical semiconductor channel.

7. The three-dimensional memory device of claim 1 , wherein a top surface of the III-V compound semiconductor pedestal is located above a horizontal plane including a top surface of a bottommost one of the electrically conductive layers.

8. The three-dimensional memory device of claim 7 , further comprising a tubular dielectric spacer laterally surrounding, and contacting, the III-V compound semiconductor pedestal, wherein the tubular dielectric spacer is formed of an oxide of a III-V compound material of the III-V compound semiconductor pedestal.

9. The three-dimensional memory device of claim 1 , further comprising:

a III-V compound semiconductor source region comprising a doped III-V compound material and contacting a top surface of the III-V compound substrate semiconductor layer;

an insulating spacer contacting sidewalls of the alternating stack; and

a contact via structure laterally surrounded by the insulating spacer and contacting a top surface of the III-V compound semiconductor source region.

10. The three-dimensional memory device of claim 9 , wherein the III-V compound semiconductor source region comprises a graded III-V compound semiconductor material having a vertical compositional gradient that provides a variable band gap that decreases with a vertical distance from an interface with the III-V compound substrate semiconductor layer.

11. The three-dimensional memory device of claim 10 , wherein:

the III-V compound substrate semiconductor layer comprises gallium arsenide; and

the graded III-V compound semiconductor material comprises a continuously or step wise graded indium gallium arsenide.

12. The three-dimensional memory device of claim 1 , wherein the memory film comprises

a tunneling dielectric layer contacting the vertical semiconductor channel;

a charge storage layer in contact with the tunneling dielectric layer; and

a blocking dielectric layer located between the charge storage layer and the electrically conductive layers.

13. The three-dimensional memory device of claim 1 , wherein:

the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layer within the alternating stack;

the terrace region comprises stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack;

a retro-stepped dielectric material portion overlies the stepped surfaces; and

contact via structures vertically extend through the retro-stepped dielectric material portion and contacts a top surface of a respective one of the electrically conductive layers.

14. A method of forming a three-dimensional memory device, comprising:

forming a III-V compound substrate semiconductor layer over a substrate;

forming an alternating stack of insulating layers and spacer material layers over the III-V compound substrate semiconductor layer, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;

forming a memory opening vertically extending through the alternating stack;

forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure is formed by:

forming a III-V compound semiconductor pedestal on the III-V compound substrate semiconductor layer;

forming a memory film in the memory opening; and

forming a vertical III-V compound semiconductor channel on the memory film;

wherein:

the substrate comprises a single crystalline silicon layer; and

the method further comprises forming a germanium-containing buffer layer on top of the single crystalline silicon layer, wherein the III-V compound substrate semiconductor layer is formed over the germanium-containing buffer layer.

15. The method of claim 14 , wherein:

the vertical semiconductor channel comprises a III-V compound semiconductor channel material;

the III-V compound substrate semiconductor layer is single crystalline; and

the III-V compound semiconductor pedestal is formed by selectively growing a single crystalline III-V compound semiconductor material from a physically exposed portion of a top surface of the III-V compound substrate semiconductor layer at a bottom of the memory opening.

16. The method of claim 14 , wherein the memory opening fill structure comprises a drain region formed at an upper end of the vertical semiconductor channel, wherein:

the III-V compound semiconductor pedestal and the III-V compound substrate semiconductor layer have a doping of a first conductivity type; and

the drain region has a doping of a second conductivity type that is an opposite of the first conductivity type.

17. The method of claim 14 , further comprising:

forming backside recesses by removing the spacer material layers selective to the insulating layers and the III-V compound semiconductor pedestal;

forming a tubular dielectric spacer by oxidizing a surface portion of the III-V compound semiconductor pedestal; and

forming the electrically conductive layers in the backside recesses.

18. The method of claim 14 , further comprising:

forming a backside trench through the alternating stack, wherein a top surface of the III-V compound substrate semiconductor layer is physically exposed; and

forming a III-V compound semiconductor source region comprising a doped III-V compound material on the top surface of the III-V compound substrate semiconductor layer, wherein the III-V compound semiconductor source region comprises a graded III-V compound semiconductor material having a vertical compositional gradient that provides a variable band gap that decreases with a vertical distance from an interface with the III-V compound substrate semiconductor layer.

19. A method of forming a three-dimensional memory device, comprising:

forming a III-V compound substrate semiconductor layer over a substrate;

forming an alternating stack of insulating layers and spacer material layers over the III-V compound substrate semiconductor layer, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;

forming a memory opening vertically extending through the alternating stack;

forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure is formed by:

forming a III-V compound semiconductor pedestal on the III-V compound substrate semiconductor layer;

forming a memory film in the memory opening; and

forming a vertical III-V compound semiconductor channel on the memory film;

forming a backside trench through the alternating stack, wherein a top surface of the III-V compound substrate semiconductor layer is physically exposed; and

forming a III-V compound semiconductor source region comprising a doped III-V compound material on the top surface of the III-V compound substrate semiconductor layer, wherein the III-V compound semiconductor source region comprises a graded III-V compound semiconductor material having a vertical compositional gradient that provides a variable band gap that decreases with a vertical distance from an interface with the III-V compound substrate semiconductor layer.

20. A three-dimensional memory device, comprising:

a substrate comprising a III-V compound substrate semiconductor layer;

an alternating stack of insulating layers and electrically conductive layers located over the III-V compound substrate semiconductor layer;

a memory opening vertically extending through the alternating stack; and

a memory opening fill structure located in the memory opening and comprising a III-V compound semiconductor pedestal in contact with the III-V compound substrate semiconductor layer, a vertical semiconductor channel, a memory film located adjacent to the vertical semiconductor channel, and a drain region located at an upper end of the vertical semiconductor channel;

wherein:

the III-V compound substrate semiconductor layer is single crystalline;

the III-V compound semiconductor pedestal is epitaxially aligned to the III-V compound substrate semiconductor layer;

the vertical semiconductor channel comprises a III-V compound semiconductor channel material;

the III-V compound semiconductor pedestal and the III-V compound substrate semiconductor layer have a doping of a first conductivity type;

the drain region has a doping of a second conductivity type that is an opposite of the first conductivity type;

the III-V compound semiconductor channel material comprises polycrystalline gallium arsenide or indium gallium arsenide; and

the drain region comprises a graded III-V compound semiconductor material having a compositional gradient that provides a variable band gap that decreases with a distance from an interface with the vertical semiconductor channel.

21. A three-dimensional memory device, comprising:

a substrate comprising a III-V compound substrate semiconductor layer;

an alternating stack of insulating layers and electrically conductive layers located over the III-V compound substrate semiconductor layer;

a memory opening vertically extending through the alternating stack;

a memory opening fill structure located in the memory opening and comprising a III-V compound semiconductor pedestal in contact with the III-V compound substrate semiconductor layer, a vertical semiconductor channel, and a memory film located adjacent to the vertical semiconductor channel;

a III-V compound semiconductor source region comprising a doped III-V compound material and contacting a top surface of the III-V compound substrate semiconductor layer;

an insulating spacer contacting sidewalls of the alternating stack; and

a contact via structure laterally surrounded by the insulating spacer and contacting a top surface of the III-V compound semiconductor source region;

wherein the III-V compound semiconductor source region comprises a graded III-V compound semiconductor material having a vertical compositional gradient that provides a variable band gap that decreases with a vertical distance from an interface with the III-V compound substrate semiconductor layer.