Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same

1. A three-dimensional memory device comprising:

at least one alternating stack of insulating layers and electrically conductive layers located over a substrate;

a memory opening vertically extending through the at least one alternating stack; and

a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel comprising a III-V compound semiconductor channel material having a doping of a first conductivity type, a memory film located adjacent to the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material having a doping of a second conductivity type that is an opposite of the first conductivity type and having a compositional gradient therein.

2. The three-dimensional memory device of claim 1 , wherein:

the III-V compound semiconductor channel material has a fixed band gap that is uniform throughout the vertical semiconductor channel; and

the drain region has a variable band gap that varies within the drain region.

3. The three-dimensional memory device of claim 2 , wherein the variable band gap of the drain region monotonically decreases within the drain region with a distance from an interface with the vertical semiconductor channel.

4. The three-dimensional memory device of claim 3 , wherein:

the III-V compound semiconductor channel material comprises a doped gallium arsenide channel material; and

the drain region comprises at least one doped graded indium gallium arsenide layer.

5. The three-dimensional memory device of claim 4 , wherein the drain region comprises a plurality of discrete doped indium gallium arsenide layers having an indium concentration which increases within the drain region with a distance from an interface with the vertical semiconductor channel.

6. The three-dimensional memory device of claim 4 , wherein the drain region comprises a doped indium gallium arsenide layer having a graded indium concentration which increases within the drain region with a distance from an interface with the vertical semiconductor channel.

7. The three-dimensional memory device of claim 3 , wherein:

the III-V compound semiconductor channel material comprises a doped indium gallium arsenide channel material; and

the drain region comprises at least one doped graded indium gallium arsenide layer having a higher indium concentration than the III-V compound semiconductor channel material.

8. The three-dimensional memory device of claim 1 , wherein:

the vertical semiconductor channel comprises a cylindrical inner sidewall, a cylindrical outer sidewall, and an annular top surface extending between the cylindrical inner sidewall and the cylindrical outer sidewall; and

the drain region contacts the annular top surface and an upper portion of the cylindrical inner sidewall of the vertical semiconductor channel.

9. The three-dimensional memory device of claim 8 , wherein:

the memory opening fill structure comprises a dielectric core located within the vertical semiconductor channel and contacting the inner cylindrical sidewall of the vertical semiconductor channel; and

the drain region contacts a top surface of the dielectric core.

10. The three-dimensional memory device of claim 1 , wherein:

the substrate comprises:

a single crystalline silicon layer;

a germanium-containing buffer layer located on top of the single crystalline silicon layer; and

a III-V compound substrate semiconductor layer located over the germanium-containing buffer layer; and

the memory opening fill structure comprises a III-V compound semiconductor pedestal located between the vertical semiconductor channel and the III-V compound substrate semiconductor layer.

11. The three-dimensional memory device of claim 10 , further comprising:

a III-V compound semiconductor source region comprising a doped graded III-V compound material contacting a top surface of III-V compound substrate semiconductor layer;

an insulating spacer contacting sidewalls of the at least one alternating stack; and

a contact via structure laterally surrounded by the insulating spacer and contacting a top surface of the III-V compound semiconductor source region.

12. The three-dimensional memory device of claim 1 , further comprising a source-level contact layer overlying the substrate and contacting an outer sidewall of the vertical semiconductor channel.

13. The three-dimensional memory device of claim 12 , wherein the source-level contact layer comprises:

a graded III-V compound semiconductor source region having a doping of an opposite conductivity type from the vertical semiconductor channel and contacting the outer sidewall of the vertical semiconductor channel; and

an annular metal germanosilicide portion contacting and laterally surrounding the III-V compound semiconductor source region.

14. The three-dimensional memory device of claim 1 , wherein the memory film comprises:

a tunneling dielectric layer contacting the vertical semiconductor channel;

a charge storage layer in contact with the tunneling dielectric layer; and

a blocking dielectric layer located between the charge storage layer and the electrically conductive layers.

15. A method of forming a three-dimensional memory device, comprising:

forming at least one alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;

forming a memory opening vertically extending through the alternating stack;

forming a memory film in the memory opening;

forming a vertical semiconductor channel comprising a III-V compound semiconductor channel material having a doping of a first conductivity type on the memory film; and

forming a drain region including a graded III-V compound semiconductor material on the vertical semiconductor channel, wherein the drain region has a doping of a second conductivity type that is an opposite of the first conductivity type and has a compositional gradient therein.

16. The method of claim 15 , wherein the graded III-V compound semiconductor material comprises at least one indium gallium arsenide material and the III-V semiconductor channel material comprises gallium arsenide or indium gallium arsenide having a lower indium concentration than the graded III-V compound semiconductor material.

17. The method of claim 15 , further comprising:

depositing a layer stack including III-V compound semiconductor material layers having different material compositions over the vertical semiconductor channel; and

removing portions of the layer stack located outside the memory opening, wherein a remaining portion of the layer stack located in an upper portion of the memory opening comprises the drain region.

18. The method of claim 17 , wherein the III-V compound semiconductor material layers in the layer stack have different band gaps that decrease with a distance from an interface between the drain region and the vertical semiconductor channel.

19. The method of claim 15 , further comprising:

forming a III-V compound substrate semiconductor layer over the substrate, wherein the at least one alternating stack is formed over the III-V compound substrate semiconductor layer; and

forming a III-V compound semiconductor pedestal on the III-V compound substrate semiconductor layer at a bottom portion of the memory opening,

wherein the vertical semiconductor channel comprises a III-V compound semiconductor channel material and is formed directly on the III-V compound semiconductor pedestal.

20. The method of claim 15 , further comprising:

forming a source-level sacrificial layer over the substrate, wherein the at least one alternating stack is formed over the source-level sacrificial material layer, and the vertical semiconductor channel extends into the source-level sacrificial layer;

forming a source cavity by removing the source-level sacrificial layer, wherein an outer sidewall of the vertical semiconductor channel is physically exposed to the source cavity;

forming a III-V compound semiconductor source region having a doping of an opposite conductivity type as the vertical semiconductor channel and contacting the outer sidewall of the vertical semiconductor channel; and

forming an annular metal germanosilicide portion contacting and laterally surrounding the III-V compound semiconductor source region.