IP Library Granted Patent US 11,004,869
Granted Patent B2
US 11,004,869 · App. 16/894,939 · Granted May 11, 2021

Semiconductor device

Inventors: Shunpei Yamazaki (Tokyo, JP); Kensuke Yoshizumi (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1207H01L27/04H01L27/0688H01L27/108H01L27/1156H01L29/42384G11C16/10H01L21/84H01L27/10805H01L27/11521H01L27/11551H01L27/1203H01L29/24
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Quick Facts
Patent No.
US 11,004,869
App. No.
16/894,939
Granted
May 11, 2021
Kind
B2
Abstract

A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.

Claims (23)

1. A semiconductor device, comprising:

a plurality of memory cells stacked over a layer comprising a driving circuit,

wherein each of the memory cells comprises:

a first transistor;

a second transistor; and

a capacitor;

wherein a gate electrode of the first transistor is electrically connected to one of electrodes of the capacitor and to one of a source electrode and a drain electrode of the second transistor,

wherein, in a plane view, a semiconductor layer of the second transistor and a dielectric of the capacitor do not protrude from the gate electrode of the first transistor, and

a channel formation region of the second transistor comprises an oxide semiconductor.

2. The semiconductor device according to claim 1 , wherein the dielectric of the capacitor comprises the same material as the semiconductor layer of the second transistor.

3. The semiconductor device according to claim 1 ,

wherein the oxide semiconductor is an In—Ga—Zn-based oxide.

4. The semiconductor device according to claim 1 ,

wherein each of the first transistor and the second transistor is electrically connected to the driving circuit through a connection electrode layer.

5. The semiconductor device according to claim 1 , further comprising an insulating layer over a first memory cell of the plurality of the memory cells, and a second memory cell of the plurality of the memory cells over the insulating layer.

6. The semiconductor device according to claim 5 ,

wherein the insulating layer comprises a low-dielectric insulating material.

7. The semiconductor device according to claim 1 ,

wherein the semiconductor layer of the second transistor has cylindrical shape.

8. The semiconductor device according to claim 1 ,

wherein the dielectric of the capacitor has cylindrical shape.

9. The semiconductor device according to claim 1 ,

wherein a channel direction of the first transistor is perpendicular to a channel direction of the second transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2020
From: YAMAZAKI, SHUNPEI; YOSHIZUMI, KENSUKE
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 052861/0812 →
Priority Claims (1)
JP 2012-044109 · Feb 29, 2012 · national
Continuity (6)
Continuation 16539237 · Aug 13, 2019
Continuation 16048412 · Jul 30, 2018
Continuation 15671216 · Aug 8, 2017
Continuation 15092674 · Apr 7, 2016
Continuation 13768753 · Feb 15, 2013
Related Publication 20200303422A1 · Sep 24, 2020