Phase locked loop circuit with oscillator signal based on switched impedance network
Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.
1. A phase locked loop circuit comprising: comparison circuitry to receive a reference signal and an oscillation signal and to generate an error signal according to a relationship between the reference signal and the oscillation signal; a loop filter to receive an output of the comparison circuitry, the loop filter having an impedance network that is switched as a function of the error signal so as to vary impedance properties of the impedance network; and oscillation circuitry to receive an output of the impedance network and to responsively generate an output signal; wherein the oscillation signal is a function of the output signal.
2. The phase locked loop circuit of claim 1 , wherein the comparison circuitry comprises a phase detector that is to produce an up/down signal as a function of phase error between the reference signal and the oscillation signal, and wherein the oscillation circuitry comprises a voltage controlled oscillator that is driven according to an accumulation of integrated phase error between the oscillation signal and the reference signal.
3. The phase locked loop circuit of claim 2 , wherein the impedance network comprises at least one metal oxide semiconductor (MOS) device to be switched according to pulses of a control signal driven as a function of change in sign of the up/down signal.
4. The phase locked loop circuit of claim 3 , wherein the impedance network comprises at least one polysilicon resistor coupled in series with the MOS device, an effective resistance of the impedance network being dependent on the at least one polysilicon resistor.
5. The phase locked loop circuit of claim 1 , wherein the comparison circuitry comprises a phase frequency detector that is to drive an accumulator to adjust control of the oscillation circuitry at separate adjustment rates for each of phase difference and frequency difference between the reference signal and the oscillation signal.
6. The phase locked loop circuit of claim 1 , wherein the comparison circuitry comprises a digital phase detector circuit.
7. The phase locked loop circuit of claim 1 , wherein the impedance network comprises at least one resistor, at least one capacitor and at least one switch, and wherein the switch is to be switched at a rate such that the impedance network reduces 1/f noise of the oscillation circuitry, where f is a frequency of oscillation of at least one of the reference signal and the oscillation signal.
8. The phase locked loop circuit of claim 1 , wherein the phase locked loop circuit further comprises frequency-divider circuitry to divide the output signal by a factor of at least four, to generate the oscillation signal.
9. The phase locked loop circuit of claim 1 , wherein the impedance network is a resistance network.
10. The phase locked loop circuit of claim 1 , wherein:
the phase locked loop circuit further comprises at least one adjustable capacitor and circuitry to selectively adjust an effective capacitance provided by the at least one adjustable capacitor; and
a loop bandwidth of the phase locked loop circuit is dependent on the effective capacitance.
11. The phase locked loop circuit of claim 1 , wherein the impedance network is to be switched according to a pulsed control signal having a pulse duration less than an RC time constant of the impedance network.
12. An integrated circuit, comprising:
a chip;
a phase locked loop circuit on the chip;
the phase locked loop circuit comprising
comparison circuitry to receive a reference signal and an oscillation signal and to generate an error signal according to a relationship between the reference signal and the oscillation signal,
a loop filter to receive an output of the comparison circuitry, the loop filter having an impedance network that is switched as a function of the error signal so as to vary impedance properties of the impedance network, and
oscillation circuitry to receive an output of the impedance network and to responsively generate an output signal;
wherein the oscillation signal is a function of the output signal.
13. The integrated circuit of claim 12 , wherein the comparison circuitry comprises a phase detector that is to produce an up/down signal as a function of phase error between the reference signal and the oscillation signal, and wherein the oscillation circuitry comprises a voltage controlled oscillator that is driven according to an accumulation of integrated phase error between the oscillation signal and the reference signal.
14. The integrated circuit of claim 13 , wherein the impedance network comprises at least one metal oxide semiconductor (MOS) device to be switched according to pulses of a control signal driven as a function of change in sign of the up/down signal.
15. The integrated circuit of claim 14 , wherein the impedance network comprises at least one polysilicon resistor coupled in series with the MOS device, an effective resistance of the impedance network dependent on the at least one polysilicon resistor.
16. The integrated circuit of claim 12 , wherein the comparison circuitry comprises a phase frequency detector that is to drive an accumulator to adjust control of the oscillation circuitry at separate adjustment rates for each of phase difference and frequency difference between the reference signal and the oscillation signal.
17. The integrated circuit of claim 12 , wherein the comparison circuitry comprises a digital phase detector circuit.
18. The integrated circuit of claim 12 , wherein the impedance network comprises at least one resistor, at least one capacitor and at least one switch, and wherein the switch is to be switched at a rate such that the impedance network reduces 1/f noise of the oscillation circuitry, where f is a frequency of oscillation of at least one of the reference signal and the oscillation signal.
19. The integrated circuit of claim 12 , wherein:
the phase locked loop circuit further comprises at least one adjustable capacitor and circuitry to selectively adjust an effective capacitance provided by the at least one adjustable capacitor; and
a loop bandwidth of the phase locked loop circuit is dependent on the effective capacitance.
20. The integrated circuit of claim 12 , wherein the impedance network is to be switched according to a pulsed control signal having a pulse duration less than an RC time constant of the impedance network.
21. A method of operation in a phase locked loop circuit having comparison circuitry, a loop filter having an impedance network, and oscillation circuitry, the method comprising:
comparing a reference signal and an oscillation signal with the comparison circuitry and responsively generating an error signal according to a relationship between the reference signal and the oscillation signal;
receiving an output of the comparison circuitry with the loop filter and using an output of the loop filter to control the oscillation circuitry; and
switching the impedance network as a function of the error signal so as to vary impedance properties of the impedance network and thereby adjust the output of the loop filter;
wherein the oscillation signal is a function of the output signal.