Neighbor word line compensation full sequence program scheme

1. A storage device, comprising:

a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines; and

a controller, coupled to the non-volatile memory, configured to:

determine data states for a first set of memory cells of a neighboring word line of the set of word lines, each of the data states being any of a plurality of data states that the first set of memory cells is configured to store, the neighboring word line being adjacent to a selected word line of the set of word lines;

determine a bit line voltage bias and a sense time for a memory cell of a second set of memory cells of the selected word line based on a data state determined for a memory cell, of the first set of memory cells, that is adjacent to the memory cell of the second set of memory cells, wherein determining the bit line voltage bias and the sense time is determined for each memory cell of the second set of memory cells; and

perform a verify operation on the selected word line using the bit line voltage bias and the sense time determined for each memory cell of the second set of memory cells to verify if each memory cell of the second set of memory cells has a threshold voltage above a verify voltage.

2. The storage device as set forth in claim 1 , wherein the controller is further configured to determine the bit line voltage bias based on the data state being of a data state set comprising one or more data states of the plurality of data states that are higher than one or more remaining data states of the plurality of data states, wherein the bit line voltage bias is lower than a bit line voltage bias used in a read operation performed on the second set of memory cells.

3. The storage device as set forth in claim 2 , wherein the controller is further configured to determine the sense time based on the data state being of the data state set, wherein the sense time is lower than a sense time used in the read operation performed on the second set of memory cells.

4. The storage device as set forth in claim 1 , wherein the controller is further configured to determine the bit line voltage bias based on the data state being of a data state set comprising one or more data states of the plurality of data states that are lower than one or more remaining data states of the plurality of data states, wherein the bit line voltage bias is higher than a bit line voltage bias used in a read operation performed on the second set of memory cells.

5. The storage device as set forth in claim 4 , wherein the controller is further configured to determine the sense time based on the data state being of the data state set, wherein the sense time is higher than a sense time used in the read operation performed on the second set of memory cells.

6. The storage device as set forth in claim 1 , wherein performing the verify operation on the selected word line is performed using a same word line bias voltage.

7. The storage device as set forth in claim 1 , wherein the controller is further configured to determine the bit line voltage bias and the sense time based on a data state of the memory cell of the second set of memory cells of the selected word line or a data state determined for a memory cell of another set of memory cells of another neighboring word line of the selected word line, the other neighboring word line of the set of word lines.

8. A method of operating a memory apparatus including a plurality of memory cells, the method comprising the steps of:

determining data states for a first set of memory cells of a neighboring word line of the set of word lines, each of the data states being any of a plurality of data states that the first set of memory cells is configured to store, the neighboring word line being adjacent to a selected word line of the set of word lines;

determining a bit line voltage bias and a sense time for a memory cell of a second set of memory cells of the selected word line based on a data state determined for a memory cell, of the first set of memory cells, that is adjacent to the memory cell of the second set of memory cells, wherein determining the bit line voltage bias and the sense time is determined for each memory cell of the second set of memory cells; and

performing a verify operation on the selected word line using the bit line voltage bias and the sense time determined for each memory cell of the second set of memory cells to verify if each memory cell of the second set of memory cells has a threshold voltage above a verify voltage.

9. The method as set forth in claim 8 , further including the steps of:

determining the bit line voltage bias based on the data state being of a data state set comprising one or more data states of the plurality of data states that are higher than one or more remaining data states of the plurality of data states, wherein the bit line voltage bias is lower than a bit line voltage bias used in a read operation performed on the second set of memory cells.

10. The method as set forth in claim 9 , further including the steps of:

determining the sense time based on the data state being of the data state set, wherein the sense time is lower than a sense time used in the read operation performed on the second set of memory cells.

11. The method as set forth in claim 8 , further including the steps of:

determining the bit line voltage bias based on the data state being of a data state set comprising one or more data states of the plurality of data states that are lower than one or more remaining data states of the plurality of data states, wherein the bit line voltage bias is higher than a bit line voltage bias used in a read operation performed on the second set of memory cells.

12. The method as set forth in claim 11 , further including the steps of:

determining the sense time based on the data state being of the data state set, wherein the sense time is higher than a sense time used in the read operation performed on the second set of memory cells.

13. The method as set forth in claim 8 , wherein performing the verify operation on the selected word line is performed using a same word line bias voltage.

14. The method as set forth in claim 8 , further including the steps of:

determining the bit line voltage bias and the sense time based on a data state of the memory cell of the second set of memory cells of the selected word line or a data state determined for a memory cell of another set of memory cells of another neighboring word line of the selected word line, the other neighboring word line of the set of word lines.

15. A controller in communication with a plurality of memory cells of a memory apparatus, the controller configured to:

determine data states for a first set of memory cells of a neighboring word line of the set of word lines, each of the data states being any of a plurality of data states that the first set of memory cells is configured to store, the neighboring word line being adjacent to a selected word line of the set of word lines;

determine a bit line voltage bias and a sense time for a memory cell of a second set of memory cells of the selected word line based on a data state determined for a memory cell, of the first set of memory cells, that is adjacent to the memory cell of the second set of memory cells, wherein determining the bit line voltage bias and the sense time is determined for each memory cell of the second set of memory cells; and

perform a verify operation on the selected word line using the bit line voltage bias and the sense time determined for each memory cell of the second set of memory cells to verify if each memory cell of the second set of memory cells has a threshold voltage above a verify voltage.

16. The controller as set forth in claim 15 , wherein the controller is further configured to:

determine the bit line voltage bias based on the data state being of a data state set comprising one or more data states of the plurality of data states that are higher than one or more remaining data states of the plurality of data states, wherein the bit line voltage bias is lower than a bit line voltage bias used in a read operation performed on the second set of memory cells.

17. The controller as set forth in claim 16 , wherein the controller is further configured to:

determine the sense time based on the data state being of the data state set, wherein the sense time is lower than a sense time used in the read operation performed on the second set of memory cells.

18. The controller as set forth in claim 15 , wherein the controller is further configured to:

determine the bit line voltage bias based on the data state being of a data state set comprising one or more data states of the plurality of data states that are lower than one or more remaining data states of the plurality of data states, wherein the bit line voltage bias is higher than a bit line voltage bias used in a read operation performed on the second set of memory cells.

19. The controller as set forth in claim 18 , wherein the controller is further configured to:

determine the sense time based on the data state being of the data state set, wherein the sense time is higher than a sense time used in the read operation performed on the second set of memory cells.

20. The controller as set forth in claim 15 , wherein performing the verify operation on the selected word line is performed using a same word line bias voltage.