Double-sided integrated circuit transistor structures with depopulated bottom channel regions
Integrated circuitry comprising interconnect metallization on both front and back sides of a gate-all-around (GAA) transistor structure lacking at least one active bottom channel region. Bottom channel regions may be depopulated from a GAA transistor structure following removal of a back side substrate that exposes an inactive portion of a semiconductor fin. During back-side processing, one or more bottom channel region may be removed or rendered inactive through dopant implantation. Back-side processing may then proceed with the interconnection of one or more terminal of the GAA transistor structures through one or more levels of back-side interconnect metallization.
1 . An integrated circuit (IC) structure, comprising:
a first interconnect metallization level;
a second interconnect metallization level;
first and second transistor structures between the first interconnect metallization level and the second interconnect metallization level, wherein:
the first transistor structure comprises:
a first gate electrode adjacent to a first stack of a first number of channel regions and an inactive channel material; and
a first source region coupled to a first drain region through the first number of channel regions, the first source region and the first drain region having a first conductivity type;
the second transistor structure comprises:
a second gate electrode adjacent to a second stack of a second number of channel regions, the second number of channel regions greater than the first number of channel regions; and
a second source region coupled to a second drain region through the second number of channel regions, the second source region and the second drain region having a second conductivity type, complementary to the first conductivity type;
a first spacing between the second interconnect metallization level and a nearest one of the first number of channel regions is greater than a second spacing between the second interconnect metallization level and a nearest one of the second number of channel regions;
the inactive channel material is substantially coplanar with the nearest one of the second number of channel regions and is within the first spacing; and
the inactive channel material is a semiconductor material having the second conductivity type with a second impurity concentration exceeding a first impurity concentration in the first number of channel regions; and
a monocrystalline material between the second interconnect metallization level and the nearest one of the first number of channel regions, wherein the monocrystalline material is also between the second interconnect metallization level and the nearest one of the second number of channel regions.
2 . The IC structure of claim 1 , wherein the channel regions of the first number of channel regions have a first channel length between the first source region and the first drain region and wherein the semiconductor material also has the first channel length.
3 . The IC structure of claim 1 , wherein:
first transistor structure is a PMOS transistor structure and the first conductivity type is p-type;
the second transistor structure is an NMOS transistor structure and the second conductivity type is n-type;
the first impurity concentration comprises at least one of P, Ar, or Sb; and
the first impurity concentration is at least 1e19cm−3.
4 . The IC structure of claim 1 , wherein the monocrystalline material has a third impurity concentration, lower than the second impurity concentration.
5 . A computer system, comprising:
a power supply; and
an IC die coupled to the power supply, the IC die comprising the integrated circuit (IC) structure of claim 1 .
6 . The computer system of claim 5 , further comprising a battery coupled to the power supply.
7 . An integrated circuit (IC) structure, comprising:
a first interconnect metallization level;
a second interconnect metallization level;
first and second transistor structures between the first interconnect metallization level and the second interconnect metallization level, wherein:
the first transistor structure comprises a first gate electrode adjacent to a first stack of a first number of channel regions;
the second transistor structure comprises a second gate electrode adjacent to a second stack of a second number of channel regions, the second number of channel regions greater than the first number of channel regions; and
a first spacing between the second interconnect metallization level and a nearest one of the first number of channel regions is greater than a second spacing between the second interconnect metallization level and a nearest one of the second number of channel regions;
individual ones of the first number of channel regions are substantially coplanar with corresponding ones of the second number of channel regions; and
a monocrystalline material between the second interconnect metallization level and the nearest one of the second number of channel regions.
8 . The IC structure of claim 7 , wherein the first spacing comprises an inactive channel material substantially coplanar with the nearest one of the second number of channel regions and is within the first spacing.
9 . The IC structure of claim 7 , wherein the first interconnect metallization level is over a top of the first and second transistor structures and wherein the second interconnect metallization level is under a bottom of the first and second transistor structures.
10 . The IC structure of claim 7 , wherein the first number of channel regions is one fewer than the second number of channels regions.
11 . An integrated circuit (IC) structure, comprising:
a first interconnect metallization level;
a second interconnect metallization level;
first and second transistor structures between the first interconnect metallization level and the second interconnect metallization level, wherein:
the first transistor structure comprises:
a first gate electrode adjacent to a first stack of a first number of channel regions and an inactive channel material; and
a first source region coupled to a first drain region through the first number of channel regions;
the second transistor structure comprises:
a second gate electrode adjacent to a second stack of a second number of channel regions, the second number of channel regions greater than the first number of channel regions; and
a second source region coupled to a second drain region through the second number of channel regions;
a first spacing between the second interconnect metallization level and a nearest one of the first number of channel regions is greater than a second spacing between the second interconnect metallization level and a nearest one of the second number of channel regions;
the inactive channel material is substantially coplanar with the nearest one of the second number of channel regions and is within the first spacing; and
a monocrystalline material between the second interconnect metallization level and the nearest one of the first number of channel regions, wherein the monocrystalline material is also between the second interconnect metallization level and the nearest one of the second number of channel regions.
12 . The IC structure of claim 11 , wherein:
the first source region and the first drain region have a first conductivity type;
the second source region and the second drain region have a second conductivity type, complementary to the first conductivity type;
the inactive channel material has the second conductivity type with a second impurity concentration exceeding a first impurity concentration in the first number of channel regions.