Gas phase treatment for manufacturing semiconductor structure
A method for manufacturing a semiconductor structure includes trimming a semiconductor region using a gaseous halogen-based etchant such that the trimmed semiconductor region has a first part and a second part which is formed on the first part and which has a halogen-terminated trimmed surface, and treating the halogen-terminated trimmed surface of the second part using a gaseous oxidant including hydrogen and oxygen such that the second part is oxidized to form an oxidized part, and such that the halogen-terminated trimmed surface is converted into a hydroxyl group-terminated surface of the oxidized part.
1 . A method for manufacturing a semiconductor structure which includes a transistor, comprising:
forming a patterned structure which includes
a substrate having an upper surface and a planar lower surface opposite to the upper surface,
a lower source/drain portion of the transistor disposed on the substrate,
a semiconductor region disposed on the lower source/drain portion, and
an upper source/drain portion of the transistor disposed on the semiconductor region, such that the semiconductor region extends lengthwise between the lower source/drain portion and the upper source/drain portion along a direction normal to the planar lower surface of the substrate;
after forming the patterned structure, trimming the semiconductor region using a gaseous halogen-based etchant such that the trimmed semiconductor region has a first part which serves as a channel of the transistor, and a second part which is formed on the first part and which has a halogen-terminated trimmed surface, the channel extending lengthwise between the lower source/drain portion and the upper source/drain portion along the direction normal to the planar lower surface of the substrate; and
treating the halogen-terminated trimmed surface of the second part using a gaseous oxidant including hydrogen and oxygen such that the second part is oxidized to form an oxidized part, and such that the halogen-terminated trimmed surface is converted into a hydroxyl group-terminated surface of the oxidized part.
2 . The method as claimed in claim 1 , wherein the semiconductor region is made of silicon, and the gaseous halogen-based etchant includes fluorine, chlorine, or a combination thereof, the method further comprising:
depositing a gate dielectric layer of the transistor on the oxidized part; and
forming a gate electrode of the transistor on the gate dielectric layer, the lower source/drain portion and the upper source/drain portion being respectively located at two opposite sides of the gate electrode along the direction normal to the planar lower surface of the substrate, the gate electrode including at least one metal layer and being spaced apart from the channel by the gate dielectric layer.
3 . The method as claimed in claim 2 , wherein the gaseous halogen-based etchant includes fluorine, and a precursor gas for generating the gaseous etchant includes hydrogen fluoride and nitrogen trifluoride.
4 . The method as claimed in a claim 1 , wherein a precursor gas for generating the gas oxidant includes both hydrogen gas and oxygen gas.
5 . A method for manufacturing a semiconductor structure, comprising:
forming a semiconductor portion over a substrate, the semiconductor portion extending lengthwise along a direction normal to the substrate and having a lower surface proximate to the substrate, an upper surface distal from the substrate, and an outer peripheral surface interconnecting the lower surface and the upper surface;
trimming a region of the semiconductor portion inward from the outer peripheral surface with a gaseous halogen-based etchant such that the trimmed region has an inner part and an outer part which surrounds the inner part, and which has an trimmed surface with halogen termination;
treating the trimmed surface of the outer part with a gaseous oxidant including hydrogen and oxygen such that the outer part is oxidized to form an oxidized part, and such that the trimmed surface with halogen termination is converted into a treated surface of the oxidized part with hydroxyl group termination; and
forming a dielectric portion on the oxidized part opposite to the inner part, the dielectric portion including metal elements.
6 . The method as claimed in claim 5 , wherein the region of the semiconductor portion is made of silicon, the inner part serves as a channel of a transistor, and the gaseous halogen-based etchant includes fluorine, chlorine, or a combination thereof.
7 . The method as claimed in claim 6 , wherein after trimming the region of the semiconductor portion, halogen elements from the gaseous halogen-based etchant are bonded to silicon elements at the trimmed surface.
8 . The method as claimed in a claim 7 , wherein during treating the trimmed surface, the halogen elements originally bonded to the silicon elements reacts with the gas oxidant such that the halogen elements are removed in a form of gaseous hydrogen halide, and such that the hydroxyl groups are bonded to the silicon elements.
9 . The method as claimed in claim 5 , wherein a precursor gas for generating the gaseous oxidant includes both hydrogen gas and oxygen gas.
10 . The method as claimed in claim 9 , wherein the gaseous oxidant is generated by combustion of the precursor gas using a pyrogenic external torch, the gaseous oxidant including hydroxide ions and water vapor.
11 . The method as claimed in claim 10 , wherein the trimmed surface is treated at a pressure ranging from 100 torr to 760 torr.
12 . The method as claimed in claim 11 , wherein the trimmed surface is treated at a temperature ranging from 200° C. to 400° C.
13 . The method as claimed in claim 9 , wherein the trimmed surface is treated at a predetermined pressure ranging from 0.4 torr to 20 torr.
14 . The method as claimed in claim 13 , wherein the gaseous hydrogen and the gaseous oxygen are formed into the gaseous oxidant including hydroxyl radicals, oxygen radicals and water vapor at the predetermined pressure.
15 . The method as claimed in claim 14 , wherein a carrier gas for facilitating formation of the gaseous oxidant includes argon, helium, water vapor, or combinations thereof.
16 . A method for manufacturing a semiconductor structure, comprising:
forming a patterned structure which includes
a substrate having an upper surface and a planar lower surface opposite to the upper surface,
a semiconductor portion formed over the upper surface of the substrate, the semiconductor portion including a lower region proximate to the substrate, an upper region distal from the substrate, and a middle region disposed between the lower region and the upper region, and
a lower gate spacer and an upper gate spacer respectively formed around the lower region and the upper region such that the middle region is exposed from the lower gate spacer and the upper gate spacer, a width of the middle region being greater than a width of each of the upper region and the lower region when measured along a direction parallel to the planar lower surface of the substrate;
trimming the middle region using a gaseous halogen-based etchant such that the trimmed middle region has an inner part and an outer part which surrounds the inner part, and which has a halogen-terminated trimmed surface;
treating the halogen-terminated trimmed surface of the outer part using a gaseous oxidant including hydrogen and oxygen such that the outer part is oxidized to form an interfacial layer disposed around the inner part, and such that the halogen-terminated trimmed surface is converted into a hydroxyl group-terminated treated surface of the interfacial layer; and
forming a gate dielectric layer on the interfacial layer.
17 . The method as claimed in claim 16 , wherein the patterned structure further includes
a lower source/drain portion formed in the lower region,
an upper source/drain portion formed on the upper region, and
a protection portion formed to cover the upper source/drain portion so as to prevent the upper source/drain portion from being trimmed by the gaseous halogen-based etchant.
18 . The method as claimed in claim 17 , wherein the patterned structure further includes a base structure which is formed between the substrate and the lower source/drain portion, and two isolation portions which are formed on the substrate and which are respectively located at two opposite sides of the base structure.
19 . The method as claimed in claim 16 , wherein:
the lower gate spacer and the upper gate spacer includes silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or combinations thereof;
an outer surface of one of the lower gate spacer and the upper gate spacer is coincident with a first surface, and an inner surface of the one of the lower gate spacer and the upper gate spacer is coincident with a second surface; and
during trimming the middle region, the middle region is trimmed in a direction toward the second surface.
20 . The method as claimed in claim 19 , wherein:
the middle region has an exposed surface exposed from the lower gate spacer and the upper gate spacer; and
before trimming the middle region, the exposed surface of the middle region extends between the lower gate spacer and the upper gate spacer, and is located between the first surface and the second surface.