Three-dimensional (3D) integrated circuit with passive elements formed by hybrid bonding
A three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. An example semiconductor device generally includes an integrated circuit (IC) having a first plurality of pads coupled to components of the IC, wherein a first oxide material is disposed between the first plurality of pads, and a second plurality of pads, wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads, and wherein a second oxide material is disposed between the second plurality of pads and is bonded to the first oxide material b. The semiconductor device may also include a substrate disposed above the second plurality of pads, one or more passive devices adjacent to the substrate, and one or more vias formed through the substrate, wherein at least one of the second plurality of pads is coupled to the one or more vias.
1. A semiconductor device comprising:
an integrated circuit (IC) having a first plurality of pads coupled to components of the IC, wherein a first oxide material is disposed between the first plurality of pads;
a second plurality of pads, wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads, and wherein a second oxide material is disposed between the second plurality of pads, the first oxide material being bonded to the second oxide material;
a substrate disposed above the second plurality of pads;
one or more passive devices disposed adjacent to the substrate;
one or more vias formed through the substrate, wherein:
at least one of the second plurality of pads is coupled to the one or more vias;
the one or more passive devices comprise a three-dimensional (3D) solenoid inductive element;
the one or more vias comprise a plurality of vias that are part of the 3D solenoid inductive element; and
the 3D solenoid inductive element comprises a magnetic core disposed adjacent to the plurality of vias and at least partially embedded in the substrate;
a first metal-insulator-metal (MIM) capacitor disposed above the substrate;
a second MIM capacitor disposed below the substrate and coupled to the first MIM capacitor through at least one of the one or more vias; and
an acoustic resonator at least partially embedded in the substrate and having one or more terminals electrically coupled to one or more of the second plurality of pads.
2. The semiconductor device of claim 1 , further comprising one or more second ICs at least partially embedded in the substrate.
3. The semiconductor device of claim 2 , wherein the substrate is adjacent to at least three sides of the one or more second ICs.
4. The semiconductor device of claim 1 , wherein the substrate comprises alumina and wherein the one or more vias comprise through-alumina vias (TAVs).
5. The semiconductor device of claim 1 , wherein the one or more passive devices further comprise at least one of:
a metal-insulator-metal (MIM) capacitive element;
a two-dimensional (2D) inductive element; or
another acoustic resonator.
6. The semiconductor device of claim 1 , wherein the first plurality of pads and the second plurality of pads comprise copper pads.
7. The semiconductor device of claim 1 , wherein the components of the IC comprise complementary metal-oxide-semiconductor (CMOS) components.
8. The semiconductor device of claim 1 , wherein a terminal of the one or more terminals of the acoustic resonator is coupled to the 3D solenoid inductive element via an interconnect.
9. The semiconductor device of claim 1 , wherein a die is embedded in a recess cavity of the substrate and wherein the die is implemented as the magnetic core for the 3D solenoid inductive element.
10. The semiconductor device of claim 8 , wherein the interconnect is disposed under at least a portion of the acoustic resonator.
11. The semiconductor device of claim 1 , wherein the first MIM capacitor and the second MIM capacitor are symmetric with respect to a longitudinal axis through the substrate.
12. The semiconductor device of claim 1 , wherein one or more lateral surfaces of the first MIM capacitor are aligned with one or more lateral surfaces of the second MIM capacitor.
13. The semiconductor device of claim 1 , wherein two opposing lateral surfaces of the first MIM capacitor are aligned with two opposing lateral surfaces of the second MIM capacitor.
14. The semiconductor device of claim 1 , wherein the first MIM capacitor and the second MIM capacitor have the same dimensions, including a height and a planar surface area.
15. A method for fabricating a semiconductor device, comprising:
forming an integrated circuit (IC) having a first plurality of pads coupled to components of the IC, wherein a first oxide material is disposed between the first plurality of pads;
forming one or more vias through a substrate;
forming a second plurality of pads, wherein at least one of the second plurality of pads is coupled to the one or more vias and wherein a second oxide material is disposed between the second plurality of pads;
forming one or more passive devices adjacent to the substrate, wherein:
the one or more passive devices comprise a three-dimensional (3D) solenoid inductive element;
the one or more vias comprise a plurality of vias that are part of the 3D solenoid inductive element; and
the 3D solenoid inductive element comprises a magnetic core disposed adjacent to the plurality of vias and at least partially embedded in the substrate;
forming a first metal-insulator-metal (MIM) capacitor above the substrate;
forming a second MIM capacitor below the substrate, wherein the second MIM capacitor is coupled to the first MIM capacitor through at least one of the one or more vias;
forming an acoustic resonator at least partially embedded in the substrate, wherein the acoustic resonator has one or more terminals electrically coupled to one or more of the second plurality of pads;
bonding at least a portion of the first plurality of pads to at least a portion of the second plurality of pads; and
bonding the first oxide material to the second oxide material.
16. The method of claim 15 , further comprising forming one or more second ICs at least partially embedded in the substrate, wherein the substrate is adjacent to at least three sides of one of the second ICs.
17. The method of claim 15 , wherein a terminal of the one or more terminals of the acoustic resonator is coupled to the 3D solenoid inductive element via an interconnect.
18. The method of claim 15 , wherein a die is embedded in a recess cavity of the substrate and wherein the die is implemented as the magnetic core for the 3D solenoid inductive element.
19. The method of claim 17 , wherein the interconnect is disposed under at least a portion of the acoustic resonator.
20. The method of claim 15 , wherein the first MIM capacitor and the second MIM capacitor are symmetric with respect to a longitudinal axis through the substrate.