IP Library › Granted Patent US 12,708,017
Granted Patent B2
US 12,708,017 · App. 17/930,640 · Granted Aug 11, 2026

Systems and methods for multi-tier multi-die modules

Inventors: Chandra Sekhar Mandalapu (Fort Collins, CO); Rahul Agarwal (Santa Clara, CA); Raja Swaminathan (Austin, TX)
Assignee: Advanced Micro Devices, Inc.
H10W72/0198H10W90/00H10W80/211H10W80/312H10W80/327H10W90/721H10W90/792
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Quick Facts
Patent No.
US 12,708,017
App. No.
17/930,640
Filed
Sep 8, 2022
Granted
Aug 11, 2026
Kind
B2
Art Unit
2898
USPC
257/668
Abstract

The disclosed computer-implemented method for multi-tier multi-die modules may include bonding a front side of a first plurality of dies to a first carrier, forming a first wafer; preparing a back-side surface of the first wafer for hybrid bonding; bonding a back side of a second plurality of dies to a second carrier, forming a second wafer; preparing a front-side surface of the second wafer for hybrid bonding; and hybrid bonding the first wafer with the second wafer. Various other methods, apparatuses, and systems are also disclosed.

Claims (49)

1 . An apparatus comprising:

a first tier comprising a first plurality of dies of differing die types, each of the first plurality of dies comprising:

a first front layer;

a first substrate layer;

one or more vias extending from the first front layer and through the first substrate layer; and

one or more bonding pads coupled to the one or more vias; and

a second tier comprising a second plurality of dies of differing die types, each of the second plurality of dies comprising a second front layer coupled to at least one of the one or more bonding pads, wherein the second tier is bonded to the first tier via wafer-to-wafer bonding.

2 . The apparatus of claim 1 , wherein:

the first plurality of dies were selected as known good dies prior to the wafer-to-wafer bonding; and

the second plurality of dies were selected as known good dies prior to the wafer-to-wafer bonding.

3 . The apparatus of claim 1 , further comprising a third tier comprising a third plurality of dies, the third plurality of dies comprising differing die types, wherein the third tier is bonded to the second tier.

4 . The apparatus of claim 3 , wherein the third tier is bonded to the second tier via at least one of:

a chip-on-wafer bonding process; or

a wafer-on-wafer bonding process.

5 . The apparatus of claim 1 , wherein at least one of the first tier or the second tier comprises at least six die types.

6 . The apparatus of claim 1 , wherein one or more of the first tier and second tier comprise a plurality of wafers with differing die types.

7 . The apparatus of claim 1 , wherein:

the first plurality of dies comprises a plurality of types of die; and

the second plurality of dies comprises a plurality of types of die.

8 . The apparatus of claim 1 , wherein:

a front side of a first plurality of dies is bonded to a first carrier with a chip-on-wafer bonding process, forming a first wafer; and

the first plurality of dies were selected as known good dies prior to the chip-on-wafer bonding process.

9 . The apparatus of claim 1 , wherein the first tier is attached to a third substrate.

10 . The apparatus of claim 1 , wherein:

the one or more vias include conductive material therein; and

each conductive material within the one or more vias is coupled to a bonding pad of the one or more bonding pads.

11 . The apparatus of claim 10 , wherein the first plurality of dies are bonded to the second plurality of dies by the one or more bonding pads.

12 . The apparatus of claim 1 , wherein the second tier is not attached to a third substrate.

13 . The apparatus of claim 1 , wherein:

at least one of the first plurality of dies is adjacent to a first hybrid bonding material; and

at least one of the second plurality of dies is adjacent to a second hybrid bonding material.

14 . The apparatus of claim 1 , wherein the wafer-to-wafer bonding includes bonding surface conductor materials of the first plurality of dies and each the second plurality of dies.

15 . A system comprising:

a substrate;

a first tier coupled to the substrate, the first tier comprising a first plurality of dies of differing die types, each of the first plurality of dies comprising:

a first front layer;

a first substrate layer;

one or more vias extending from the first front layer and through the first substrate layer; and

one or more bonding pads coupled to the one or more vias; and

a second tier comprising a second plurality of dies of differing die types, each of the second plurality of dies comprising a second front layer coupled to at least one of the one or more bonding pads, wherein the second tier is bonded to the first tier via wafer-to-wafer bonding.

16 . The system of claim 15 , wherein at least one of the first tier or the second tier comprises at least six die types.

17 . The system of claim 15 , wherein:

the one or more vias include conductive material therein; and

each conductive material within the one or more vias is coupled to a bonding pad of the one or more bonding pads.

18 . The system of claim 17 , wherein the first plurality of dies are bonded to the second plurality of dies by the one or more bonding pads.

19 . The system of claim 15 , wherein the first tier is attached to a substrate.

20 . The system of claim 15 , wherein:

at least one of the first plurality of dies is adjacent to a first hybrid bonding material; and

at least one of the second plurality of dies is adjacent to a second hybrid bonding material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2022
From: MANDALAPU, CHANDRA SEKHAR; SWAMINATHAN, RAJA; AGARWAL, RAHUL
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 061038/0578 →
Continuity (1)
Related Publication 20250293203A1 · Sep 18, 2025
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