IP Library Patent Application 16907520
Patent Application
App. No. 16/907,520

SEMICONDUCTOR DEVICE AND METHOD OF FORMING BACKSIDE OPENINGS FOR AN ULTRA-THIN SEMICONDUCTOR DIE

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Quick Facts
Patent No.
US None
App. No.
16/907,520
Abstract

A semiconductor substrate contains a plurality of openings extending partially into a surface of the semiconductor substrate. A conductive layer is formed with a first portion of the conductive layer over a remaining portion of the surface of the semiconductor substrate between the openings and a second portion of the conductive layer in the openings. The remaining portion of the surface of the semiconductor substrate is removed to lift-off the first portion of the conductive layer while leaving the second portion of the conductive layer in the openings. The semiconductor substrate is singulated to separate the semiconductor die leaving the second portion of the conductive layer over a surface of the semiconductor die. Alternatively, a plurality of openings is formed over each semiconductor die. A conductive layer is formed over a remaining portion of the surface of the semiconductor substrate between the openings and into the openings.

Claims (32)

1 . A method of making a semiconductor device, the method comprising:

providing a semiconductor substrate including a plurality of semiconductor die;

forming a plurality of openings over the plurality of semiconductor die, the plurality of openings extending partially into a surface of the semiconductor substrate; and

after forming the plurality of openings, forming a conductive layer on the surface of the semiconductor substrate and into the plurality of openings.

2 . The method of claim 1 , wherein the plurality of openings are arranged in multiple offset rows.

3 . The method of claim 2 , wherein a boundary of the multiple offset rows corresponds with a boundary of a respective semiconductor die of the plurality of semiconductor die.

4 . The method of claim 1 , wherein the plurality of openings comprise one of a hexagonal shape, a circular shape, a rectangular shape, a linear shape, or any combination thereof.

5 . The method of claim 1 , wherein the plurality of openings is one of a polygonal shape or an elliptical shape.

6 . The method of claim 1 , further comprising forming a support ring simultaneously with the plurality of openings.

7 . The method of claim 1 , further comprising forming a support ring separately from forming the plurality of openings.

8 . A method of making a semiconductor device, the method comprising:

providing a semiconductor substrate including a plurality of semiconductor die;

forming a plurality of openings each comprising a closed shape over the plurality of semiconductor die, the plurality of openings extending into a surface of the semiconductor substrate; and

after forming the plurality of openings, forming a conductive layer on the surface of the semiconductor substrate and into the plurality of openings.

9 . The method of claim 8 , wherein the plurality of openings are arranged in multiple offset rows.

10 . The method of claim 9 , wherein a boundary of the multiple offset rows corresponds with a boundary of a respective semiconductor die of the plurality of semiconductor die.

11 . The method of claim 8 , wherein the closed shape comprises one of a hexagonal shape, a circular shape, a rectangular shape, a linear shape, or any combination thereof.

12 . The method of claim 8 , wherein the closed shape comprises a polygonal shape or an elliptical shape.

13 . The method of claim 8 , further comprising forming a support ring simultaneously with the plurality of openings.

14 . The method of claim 8 , further comprising forming a support ring separately from forming the plurality of openings.

15 . A method of making a semiconductor device, the method comprising:

providing a semiconductor substrate including a plurality of semiconductor die;

forming a pattern of a plurality of openings each comprising a closed shape over the plurality of semiconductor die, the plurality of openings formed in a surface of the semiconductor substrate; and

after forming the pattern, forming a conductive layer on the pattern.

16 . The method of claim 15 , wherein the closed shape comprises one of a hexagonal shape, a circular shape, a rectangular shape, a linear shape, or any combination thereof.

17 . The method of claim 15 , wherein the closed shape comprises a polygonal shape or an elliptical shape.

18 . The method of claim 15 , further comprising forming a support ring simultaneously with the plurality of openings.

19 . The method of claim 15 , further comprising forming a support ring separately from forming the plurality of openings.

20 . The method of claim 15 , wherein forming the pattern further comprises:

forming the pattern on the semiconductor substrate using a photoresist;

etching the plurality of openings into the semiconductor substrate; and

removing the photoresist.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 053613, FRAME 0621 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0942 →
SECURITY INTEREST Recorded Aug 27, 2020
From: FAIRCHILD SEMICONDUCTOR CORPORATION; SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 053613/0621 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2020
From: GRIVNA, GORDON M.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 052998/0534 →