Three-dimensional memory device including III-V compound semiconductor channel layer and method of making the same
A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.
1. A method of forming a three-dimensional memory device, comprising:
providing a first assembly including a transfer substrate, a single-crystalline germanium-containing layer, and a first silicon oxide component layer;
providing a second assembly including a substrate material layer and a second silicon oxide component layer;
bonding the first silicon oxide component layer to the second silicon oxide component layer to form a silicon oxide layer;
detaching the transfer substrate from an assembly including, from bottom to top, the substrate material layer, the silicon oxide layer, and the single-crystalline germanium-containing layer;
growing a single-crystalline III-V compound semiconductor layer on the single-crystalline germanium-containing layer;
forming an alternating stack of insulating layers and spacer material layers over the single-crystalline III-V compound semiconductor layer, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;
forming memory openings through the alternating stack; and
forming memory opening fill structures in the memory openings, wherein each memory opening fill structure comprises a memory film and a vertical semiconductor channel having a bottom end that is electrically connected to the single-crystalline III-V compound semiconductor layer.
2. The method of claim 1 , further comprising separating an assembly including the single-crystalline germanium-containing layer, the single-crystalline III-V compound semiconductor layer, the alternating stack, and the memory opening fill structures from the substrate material layer at a separation surface that includes a surface of the silicon oxide layer.
3. The method of claim 2 , wherein the growing of the single-crystalline III-V compound semiconductor layer on the single-crystalline germanium-containing layer occurs after the bonding the first silicon oxide component layer to the second silicon oxide component layer to form the silicon oxide layer; and
wherein the detaching of the transfer substrate from an assembly including the substrate material layer, the silicon oxide layer, and the single-crystalline germanium-containing layer occurs after the bonding the first silicon oxide component layer to the second silicon oxide component layer.
4. The method of claim 3 , further comprising:
growing an in-process single-crystalline germanium-containing layer on the transfer substrate, wherein the first silicon oxide component layer is formed over the in-process single-crystalline germanium-containing layer;
forming a hydrogen implanted region within the in-process single-crystalline germanium-containing layer by implanting hydrogen atoms, wherein the in-process single-crystalline germanium-containing layer is divided into the single-crystalline germanium-containing layer contacting the first silicon oxide component layer and an additional single-crystalline germanium-containing layer located on the transfer substrate, and wherein the first assembly comprises the additional single-crystalline germanium-containing layer and the hydrogen implanted region.
5. The method of claim 4 , wherein detaching the transfer substrate from the assembly including the substrate material layer, the silicon oxide layer, and the single-crystalline germanium-containing layer comprises inducing bubbling of hydrogen atoms in the hydrogen implanted region, wherein a combination of the transfer substrate and the additional single-crystalline germanium-containing layer is detached from the single-crystalline germanium-containing layer.
6. The method of claim 4 , wherein:
the transfer substrate comprises a single-crystalline silicon substrate;
the in-process single-crystalline germanium-containing layer is grown on the transfer substrate by an epitaxial growth process; and
the separation surface comprises an interface between the first silicon oxide component layer and the second silicon oxide component layer.
7. The method of claim 2 , further comprising forming first dielectric material layers embedding first metal interconnect structures and first bonding pads over the alternating stack, wherein the first metal interconnect structures are electrically connected to nodes of the memory opening fill structures or the electrically conductive layers.
8. The method of claim 7 , further comprising:
forming field effect transistors on a semiconductor substrate;
forming second dielectric material layers embedding second metal interconnect structures and second bonding pads over the field effect transistors, wherein the second metal interconnect structures are electrically connected to nodes of the field effect transistors; and
bonding the second metal pads to the first metal pads, wherein the field effect transistors are located in a peripheral circuit configured to control operation of memory elements in the memory opening fill structures.
9. The method of claim 8 , wherein the assembly including the single-crystalline germanium-containing layer, the single-crystalline III-V compound semiconductor layer, the alternating stack, and the memory opening fill structures is separated from the substrate material layer after the second metal pads are bonded to the first metal pads.
10. The method of claim 8 , further comprising:
forming a first silicon nitride diffusion barrier layer on sidewalls of the first dielectric material layers, wherein a surface of the silicon oxide layer is physically exposed;
forming a second silicon nitride diffusion barrier layer on sidewalls of the second dielectric material layers; and
isotropically etching peripheral portions of the silicon oxide layer prior to separating the assembly including the single-crystalline germanium-containing layer, the single-crystalline III-V compound semiconductor layer, the alternating stack, and the memory opening fill structures from the substrate material layer.
11. The method of claim 1 , wherein each of the memory opening fill structures comprises a III-V compound semiconductor pedestal contacting a bottom end of a respective one of the vertical semiconductor channels and contacting a top surface of the single-crystalline III-V compound semiconductor layer.
12. The method of claim 11 , wherein each III-V compound semiconductor pedestal is epitaxially aligned to the single-crystalline III-V compound semiconductor layer.
13. The method of claim 12 , wherein each vertical semiconductor channel comprises a III-V compound semiconductor material.
14. The method of claim 11 , wherein:
each III-V compound semiconductor pedestal and each vertical semiconductor channel have a doping of a first conductivity type; and
the single-crystalline III-V compound semiconductor layer has a doping of the first conductivity type.
15. The method of claim 11 , wherein each memory film comprises a layer stack including a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer that contacts a respective one of the vertical semiconductor channels.
16. The method of claim 1 , wherein the silicon oxide layer is located between the substrate material layer and the single-crystalline germanium-containing layer.
17. The method of claim 1 , further comprising forming grooves on a top surface of the first silicon oxide component layer prior to bonding the first silicon oxide component layer to the second silicon oxide component layer, wherein volumes of the grooves become channels containing volumes of voids and located between the first silicon oxide component layer and the second silicon oxide component layer after formation of the silicon oxide layer.
18. The method of claim 17 , further comprising removing portions of the first silicon oxide component layer and the second silicon oxide component layer that are proximal to the channels by introducing an isotropic etchant that etches the first silicon oxide material and the second silicon oxide material after formation of the memory opening fill structures.
19. The method of claim 1 , further comprising detaching a first structure comprising the substrate material layer from a second structure comprising the single-crystalline germanium-containing layer and the alternating stack, wherein:
the first structure comprises a first portion of the silicon oxide layer; and
the second structure comprises a second portion of the silicon oxide layer.
20. The method of claim 1 , wherein:
the first silicon oxide component layer consists essentially of a first silicon oxide material;
the second silicon oxide component layer consists essentially of a second silicon oxide material; and
the step of bonding the first silicon oxide component layer to the second silicon oxide component layer comprises bonding the first silicon oxide material to the second silicon oxide material, such that the silicon oxide layer consists essentially of the first silicon oxide material and the second silicon oxide material.