IP Library › Granted Patent US 10,998,344
Granted Patent B2
US 10,998,344 · App. 16/917,601 · Granted May 4, 2021

Displays with silicon and semiconducting oxide thin-film transistors

Inventors: Vasudha Gupta (Cupertino, CA); Jae Won Choi (San Jose, CA); Shih Chang Chang (San Jose, CA); Tsung-Ting Tsai (San Jose, CA); Young Bae Park (Cupertino, CA)
Assignee: Apple Inc.
H01L27/1225G02F1/1368G02F1/13624H01L27/1222H01L27/1251H01L27/1255H01L27/3262H01L27/3272G02F1/13452G02F1/13454G02F1/13685G02F2202/104H01L29/7869
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Quick Facts
Patent No.
US 10,998,344
App. No.
16/917,601
Granted
May 4, 2021
Kind
B2
Abstract

An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.

Claims (46)

1. A display pixel comprising:

a first power supply terminal;

a second power supply terminal;

a light-emitting diode coupled between the first and second power supply terminals;

a drive transistor coupled between the first power supply terminal and the light-emitting diode;

a first switching transistor that is coupled to a gate of the drive transistor, wherein the first switching transistor is an oxide transistor;

a capacitor coupled to a first node that is interposed between the first switching transistor and the drive transistor;

a sensing line that is configured to implement a compensation scheme; and

a second switching transistor that is coupled between the sensing line and a second node that is interposed between the drive transistor and the light-emitting diode, wherein the second switching transistor is a silicon transistor.

2. The display pixel defined in claim 1 , wherein the drive transistor is an oxide transistor.

3. The display pixel defined in claim 1 , wherein the drive transistor is a silicon transistor.

4. The display pixel defined in claim 1 , wherein the second switching transistor is a p-type metal-oxide-semiconductor silicon transistor.

5. The display pixel defined in claim 1 , wherein the second switching

transistor is an n-type metal-oxide-semiconductor silicon transistor.

6. The display pixel defined in claim 1 , wherein the drive transistor has a channel formed from a layer of semiconducting oxide.

7. The display pixel defined in claim 1 , wherein the capacitor is configured to store data signals from a data line.

8. A display pixel comprising:

a first power supply terminal;

a second power supply terminal;

a light-emitting diode coupled between the first and second power supply terminals;

a drive transistor coupled between the first power supply terminal and the light-emitting diode;

a first switching transistor that is coupled to a gate of the drive transistor, wherein the first switching transistor is an oxide transistor;

a storage capacitor coupled to a first node that is interposed between the first switching transistor and the drive transistor;

a sensing line that is configured to adjust for pixel-to-pixel variations in transistor performance; and

a second switching transistor that is coupled between the sensing line and a second node that is interposed between the drive transistor and the light-emitting diode.

9. The display pixel defined in claim 8 , wherein the first switching transistor has a channel formed from a layer of semiconducting oxide and wherein the drive transistor has a channel formed from a layer of semiconducting oxide.

10. The display pixel defined in claim 9 , wherein the second switching transistor has a channel formed from a layer of silicon.

11. The display pixel defined in claim 8 , wherein the first switching transistor has a channel formed from a layer of semiconducting oxide and wherein the drive transistor has a channel formed from a layer of silicon.

12. The display pixel defined in claim 11 , wherein the second switching transistor has a channel formed from a layer of silicon.

13. The display pixel defined in claim 8 , wherein the storage capacitor is configured to store signals on the gate of the drive transistor between frames.

14. The display pixel defined in claim 8 , wherein the second switching transistor is a p-type metal-oxide-semiconductor silicon transistor.

15. The display pixel defined in claim 8 , wherein the second switching

transistor is an n-type metal-oxide-semiconductor silicon transistor.

16. A display pixel comprising:

a first power supply terminal;

a second power supply terminal;

a light-emitting diode coupled between the first and second power supply terminals;

a drive transistor coupled between the first power supply terminal and the light-emitting diode;

a first switching transistor that is coupled to a gate of the drive transistor, wherein the first switching transistor is an oxide transistor;

a sensing line; and

a second switching transistor that is coupled between the sensing line and a first node that is interposed between the drive transistor and the light-emitting diode, wherein the second switching transistor is a silicon transistor.

17. The display pixel defined in claim 16 , wherein the drive transistor is an oxide transistor.

18. The display pixel defined in claim 16 , wherein the drive transistor is a silicon transistor.

19. The display pixel defined in claim 16 , wherein the sensing line is used to implement a compensation scheme to adjust for pixel-to-pixel variations in transistor performance.

20. The display pixel defined in claim 16 , further comprising:

a storage capacitor coupled to a second node that is interposed between the first switching transistor and the drive transistor.

Continuity (7)
Continuation 16678599 · Nov 8, 2019
Continuation 16125973 · Sep 10, 2018
Continuation 15727475 · Oct 6, 2017
Continuation 14249716 · Apr 10, 2014
Continuation In Part 14228070 · Mar 27, 2014
Provisional Application 61869937 · Aug 26, 2013
Related Publication 20200335528A1 · Oct 22, 2020
Cited By (3)
US 12,396,263 US 12,543,440 US 12,707,717