Granted Patent B2

US 12,707,717 · App. 18/012,079 · Granted Aug 11, 2026

Inventors: Susumu Kawashima (Atsugi, JP); Koji Kusunoki (Isehara, JP); Kazunori Watanabe (Tokyo, JP); Satoshi Yoshimoto (Isehara, JP)

Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

H10D86/423H10K59/1213H10K59/40

Abstract

Claims (78)

1 . A display apparatus comprising:

a pixel comprising a first transistor, a second transistor, and a light-emitting device,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein a gate of the first transistor is electrically connected to a first source line,

wherein the other of the source and the drain of the second transistor is electrically connected to one electrode of the light-emitting device,

wherein a gate of the second transistor is electrically connected to a second source line,

wherein the first transistor is a p-channel transistor, and

wherein the second transistor is an n-channel transistor.

2 . The display apparatus according to claim 1 ,

wherein the first transistor comprises silicon in a channel formation region,

wherein the second transistor comprises a metal oxide in a channel formation region,

wherein the metal oxide comprises In, Zn, and M, and

wherein M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf.

3 . The display apparatus according to claim 1 ,

wherein the pixel comprises a third transistor, a fourth transistor, and a fifth transistor,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the second transistor, and

wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the second transistor.

4 . The display apparatus according to claim 3 ,

wherein the third transistor, the fourth transistor, and the fifth transistor comprise a metal oxide in channel formation regions,

wherein the metal oxide comprises In, Zn, and M, and

wherein M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf.

5 . The display apparatus according to claim 3 , further comprising a first circuit,

wherein the first circuit is configured to output a first data potential and a second data potential,

wherein one of the first data potential and the second data potential is equivalent to an input potential to the first circuit,

wherein the other of the first data potential and the second data potential is a potential obtained by binarizing the input potential,

wherein the one of the first data potential and the second data potential is input to the gate of the first transistor through the third transistor, and

wherein the other of the first data potential and the second data potential is input to the gate of the second transistor through the fourth transistor.

6 . The display apparatus according to claim 5 ,

wherein the first circuit comprises a CMOS inverter circuit which comprises a p-channel transistor containing silicon in a channel formation region and an n-channel transistor containing a metal oxide in a channel formation region,

wherein the metal oxide comprises In, Zn, and M, and

wherein M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf.

7 . An electronic device comprising the display apparatus according to claim 1 and a camera.

8 . The display apparatus according to claim 1 , further comprising a first circuit,

wherein the first circuit is configured to output a first image data and a second image data,

wherein the first image data is input to the gate of the first transistor through the first source line, and

wherein the second image data is input to the gate of the second transistor through the second source line.

9 . A display apparatus comprising:

a pixel comprising a first transistor, a second transistor, and a light-emitting device,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein a gate of the first transistor is electrically connected to a first source line,

wherein the other of the source and the drain of the second transistor is electrically connected to one electrode of the light-emitting device,

wherein a gate of the second transistor is electrically connected to a second source line,

wherein the first transistor comprises a first semiconductor layer comprising a channel formation region,

wherein the second transistor comprises a second semiconductor layer comprising a channel formation region, and

wherein a material of the first semiconductor layer is different from a material of the second semiconductor layer.

10 . The display apparatus according to claim 9 ,

wherein the first semiconductor layer comprises silicon, and

wherein the second semiconductor layer comprises a metal oxide.

11 . The display apparatus according to claim 10 ,

wherein the metal oxide comprises In, Zn, and M, and

wherein M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf.

12 . The display apparatus according to claim 9 , further comprising a first circuit,

wherein the first circuit is configured to output a first image data and a second image data,

wherein the first image data is input to the gate of the first transistor through the first source line, and

wherein the second image data is input to the gate of the second transistor through the second source line.

13 . A display apparatus comprising:

a pixel comprising a first transistor, a second transistor, a light-emitting device, and a first circuit,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to one electrode of the light-emitting device,

wherein in a first period, the first transistor is configured to operate as a driving transistor,

wherein in a second period, the second transistor is configured to operate as a driving transistor,

wherein the first circuit is configured to output a first image data and a second image data,

wherein the first image data is input to a gate of the first transistor, and

wherein the second image data is input to a gate of the second transistor.

14 . The display apparatus according to claim 13 ,

wherein the first transistor comprises a first semiconductor layer comprising a channel formation region,

wherein the second transistor comprises a second semiconductor layer comprising a channel formation region, and

wherein a material of the first semiconductor layer is different from a material of the second semiconductor layer.

15 . The display apparatus according to claim 14 ,

wherein the first semiconductor layer comprises silicon, and

wherein the second semiconductor layer comprises a metal oxide.

16 . The display apparatus according to claim 15 ,

wherein the metal oxide comprises In, Zn, and M, and

wherein M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf.

17 . The display apparatus according to claim 13 ,

wherein the first transistor is a p-channel transistor, and

wherein the second transistor is an n-channel transistor.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (80)