IP Library Granted Patent US 11,646,267
Granted Patent B2
US 11,646,267 · App. 16/941,231 · Granted May 9, 2023

Thinned semiconductor package and related methods

Inventors: Yusheng Lin (Phoenix, AZ); Takashi Noma (Ota, JP); Francis J. Carney (Mesa, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/53233H01L24/11H01L24/33
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,646,267
App. No.
16/941,231
Granted
May 9, 2023
Kind
B2
Abstract

Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

Claims (40)

1. A semiconductor package comprising:

a die having a first side and a second side opposite the first side;

a first metal layer coupled over a second metal layer, the second metal layer coupled over the first side of the die;

a tin layer coupled to the first metal layer;

a backside metal layer coupled to the second side of the die;

a mold compound coupled to the die, wherein the mold compound covers a plurality of sidewalls of the first metal layer, a plurality of sidewalls of the second metal layer, and a plurality of sidewalls of the tin layer;

wherein a surface of the mold compound is coplanar with a surface of the tin layer; and

wherein a portion of the mold compound extends to the second side of the die.

2. The semiconductor package of claim 1 , wherein a third side, a fourth side, a fifth side, and a sixth side of the die are covered by the mold compound.

3. The semiconductor package of claim 1 , wherein the backside metal layer comprises copper.

4. The semiconductor package of claim 1 , wherein the backside metal layer comprises a metal alloy comprising titanium, nickel, silver, vanadium, copper, and any combination thereof.

5. The semiconductor package of claim 1 , wherein the backside metal layer comprises at least three layers.

6. The semiconductor package of claim 5 , wherein each of the at least three layers comprise one of titanium, nickel, silver, vanadium or copper.

7. The semiconductor package of claim 1 , further comprising a second mold compound directly coupled to the second side of the die.

8. A semiconductor package comprising:

a die having a first side and a second side opposite the first side;

a plurality of bumps, each bump of the plurality of bumps comprising:

a first metal layer coupled to a second metal layer, the second metal layer coupled to the first side of the die; and

a tin layer coupled to the first metal layer; and

a backside metal layer coupled to the second side of the die; and

a mold compound coupled to the die, wherein the mold compound covers a plurality of sidewalls of the first metal layer, a plurality of sidewalls of the second metal layer, and a plurality of sidewalls of the tin layer;

wherein the mold compound extends to the second side of the die.

9. The semiconductor package of claim 8 , wherein a third side, a fourth side, a fifth side, and a sixth side of the die are covered by the mold compound.

10. The semiconductor package of claim 8 , wherein the backside metal layer comprises copper.

11. The semiconductor package of claim 8 , wherein the backside metal layer comprises a metal alloy comprising titanium, nickel, silver, vanadium, copper, and any combination thereof.

12. The semiconductor package of claim 8 , wherein the backside metal layer comprises at least three layers.

13. The semiconductor package of claim 12 , wherein each of the at least three layers comprise one of titanium, nickel, silver, vanadium or copper.

14. The semiconductor package of claim 8 , further comprising a second mold compound directly coupled to the second side of the die.

15. A semiconductor package comprising:

a die having a first side and a second side opposite the first side;

a first metal layer coupled over a second metal layer, the second metal layer coupled over the first side of the die;

a tin layer coupled to the first metal layer;

a backside metal layer coupled to the second side of the die;

a mold compound coupled to the die, wherein the mold compound covers a plurality of sidewalls of the first metal layer, a plurality of sidewalls of the second metal layer, and a plurality of sidewalls of the tin layer;

wherein a surface of the mold compound is coplanar with a surface of the tin layer; and

wherein a portion of the mold compound extends only to the backside metal layer.

16. The semiconductor package of claim 15 , wherein the backside metal layer comprises copper.

17. The semiconductor package of claim 15 , wherein the backside metal layer comprises a metal alloy comprising titanium, nickel, silver, vanadium, copper, and any combination thereof.

18. The semiconductor package of claim 15 , wherein the backside metal layer comprises at least three layers.

19. The semiconductor package of claim 18 , wherein each of the at least three layers comprise one of titanium, nickel, silver, vanadium or copper.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 054523, FRAME 0378 Recorded Aug 16, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064615/0602 →
SECURITY INTEREST Recorded Nov 25, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 054523/0378 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2020
From: LIN, YUSHENG; CARNEY, FRANCIS J.; NOMA, TAKASHI
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 053332/0741 →
Continuity (2)
Division 15921898 · Mar 15, 2018
Related Publication 20200357751A1 · Nov 12, 2020
Cited By (1)
US 12,199,041