SiC MOSFET with built-in Schottky diode

1. A Silicon Carbide (SiC) semiconductor device, comprising:

an n-type substrate;

a drift region disposed on the n-type substrate;

a p-type body region disposed on the drift region;

a vertical Junction Field Effect Transistor (JFET) region disposed on the drift region;

a Schottky contact disposed over the p-type body region and the vertical JFET region;

a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) having a source region electrically connected to the p-type body region and to the Schottky contact, a gate and gate oxide disposed at least partially on the p-type body region, and a drain contact electrically connected to the n-type substrate; and

an n-type lateral channel layer at least partially overlapping the gate oxide, the Schottky contact, the p-type body region, and the vertical JFET region, and electrically connecting the MOSFET and the vertical JFET region.

2. The SiC semiconductor device of claim 1 , wherein the n-type lateral channel layer is normally-on.

3. The SiC semiconductor device of claim 1 , wherein an extent of lateral extension of the n-type lateral channel layer in overlapping the vertical JFET region exceeds a width of a zero-bias depletion region of the vertical JFET region and enables electron flow to a non-depleted region of the vertical JFET region.

4. The SiC semiconductor device of claim 1 , wherein the n-type lateral channel layer entirely overlaps the vertical JFET region.

5. The SiC semiconductor device of claim 1 , wherein, during a flow of on-state current of the MOSFET, an inversion channel of the MOSFET is formed at a boundary of the gate oxide to the p-type body region.

6. The SiC semiconductor device of claim 1 , wherein the n-type lateral channel layer extends between the vertical JFET region and the source region of the MOSFET.

7. The SiC semiconductor device of claim 1 , further comprising:

an overgrown region extending laterally between the p-type body region and the vertical JFET region, and including the n-type lateral channel layer therein.

8. The SiC semiconductor device of claim 7 , further comprising:

a p-type channel stopper region disposed between the n-type lateral channel layer and the source region of the MOSFET,

wherein, during a flow of on-state current of the MOSFET, an inversion channel of the MOSFET is formed at a boundary of the gate oxide and the channel stopper region.

9. The SiC semiconductor device of claim 1 , wherein the Schottky contact extends laterally over the p-type body region.

10. The SiC semiconductor device of claim 1 , wherein the gate and the gate oxide are laterally spaced from, and do not overlap, the vertical JFET region.

11. The SiC semiconductor device of claim 1 , wherein a charge-balanced p-pillar and n-pillar are disposed within the drift region.

12. The SiC semiconductor device of claim 1 , further comprising an interlayer dielectric disposed between the gate and the Schottky contact.

13. The SiC semiconductor device of claim 1 , wherein the lateral channel layer provides a lateral JFET channel in series with the MOSFET that provides current-limiting during a short-circuit event.

14. A SiC semiconductor device, comprising:

a substrate of a first conductivity type;

a drift region disposed on the substrate;

a junction field effect transistor (JFET) region of the first conductivity type, the JFET region being disposed on the drift region;

a body region of a second conductivity type, the body region being disposed on the drift region and adjacent to the JFET region;

a Schottky contact disposed over the JFET region and over a portion of the body region;

a lateral channel layer of the first conductivity type, extending laterally over the body region and the JFET region, and partially adjacent to the Schottky contact; and

a MOSFET having a source region of the first conductivity type that is electrically connected to the Schottky contact, a drain region of the first conductivity type, a gate, and a gate oxide disposed over the body region, the lateral channel layer, and the source region.

15. The SiC semiconductor device of claim 14 , wherein the lateral channel layer is configured to be on under zero-bias conditions, and off at a positive turn-on voltage, of the MOSFET.

16. The SiC semiconductor device of claim 14 , wherein the Schottky contact extends laterally over an entirety of the JFET region.

17. The SiC semiconductor device of claim 14 , wherein the lateral channel layer provides current-limiting during a short-circuit event at a load of the SiC semiconductor device.

18. The SiC semiconductor device of claim 14 , wherein the gate and the gate oxide are laterally spaced from, and do not overlap, the JFET region.

19. A method of making a SiC semiconductor device, the method comprising:

providing a drift region on a SiC substrate of a first conductivity type;

providing a body region of a second conductivity type on the drift region;

providing a JFET region of the first conductivity type on the drift region and adjacent to the body region;

providing a lateral channel layer of the first conductivity type, extending laterally across the body region and the JFET region;

providing a Schottky contact laterally overlapping an entirety of the JFET region and a portion of the lateral channel layer; and

providing a MOSFET having a source region electrically connected to the body region and to the Schottky contact, a gate and gate oxide disposed at least partially on the body region and on the lateral channel layer, and a drain contact electrically connected to the substrate.

20. The method of claim 19 , further comprising doping the lateral channel layer with dopants of the first conductivity type to cause the lateral channel layer to be normally-on.