Power rails for stacked semiconductor device

1. A method, comprising:

forming a stacked semiconductor device on a first surface of a substrate, wherein the stacked semiconductor device comprises:

a first fin structure comprising a first source/drain (S/D) region;

an isolation structure on the first fin structure; and

a second fin structure above the first fin structure and in contact with the isolation structure, wherein the second fin structure comprises a second S/D region;

etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening, wherein the second surface is opposite to the first surface;

forming a dielectric barrier in the opening; and

forming an S/D contact in the opening.

2. The method of claim 1 , further comprising:

replacing the substrate with a dielectric layer;

forming an interconnect in the dielectric layer to connect to the S/D contact; and

connecting the interconnect to a power supply.

3. The method of claim 2 , wherein the replacing the substrate comprises:

removing the substrate; and

forming the dielectric layer, wherein the dielectric layer comprises silicon oxide.

4. The method of claim 1 , further comprising:

replacing the substrate with a dielectric layer;

forming an interconnect to connect to the S/D contact; and

connecting the interconnect to ground.

5. The method of claim 1 , further comprising:

forming a bonding layer on the first surface of the substrate;

bonding an other substrate to the bonding layer;

flipping the substrate on top of the other substrate; and

removing a portion of the substrate.

6. The method of claim 1 , wherein the forming the dielectric barrier comprises:

depositing a dielectric layer in the opening; and

etching a portion of the dielectric layer on the first or second S/D region.

7. The method of claim 1 , wherein the forming the S/D contact comprises:

forming a silicide layer on the first or second S/D region; and

forming a metal contact on the silicide layer.

8. The method of claim 1 , wherein the portion of the first or second S/D region comprises an epitaxial stop layer.

9. A method, comprising:

forming a stacked semiconductor device on a first surface of a substrate, wherein the stacked semiconductor device comprises:

a first fin structure comprising a first source/drain (S/D) region;

an isolation structure on the first fin structure; and

a second fin structure above the first fin structure and in contact with the isolation layer, wherein the second fin structure comprises a second S/D region;

etching a second surface of the substrate and a portion of the first S/D region to form a first opening, wherein the second surface is opposite to the first surface;

forming a first dielectric barrier in the first opening;

forming a first S/D contact in the first opening;

etching the second surface of the substrate and a portion of the second S/D region to form a second opening;

forming a second dielectric barrier in the second opening; and

forming a second S/D contact in the second opening.

10. The method of claim 9 , further comprising:

replacing the substrate with a dielectric layer;

forming a first interconnect to connect to the first S/D contact and a second interconnect to connect to the second S/D contact; and

connecting the first interconnect to a power supply and the second interconnect to ground.

11. The method of claim 10 , wherein the replacing the substrate comprises:

removing the substrate; and

forming the dielectric layer, wherein the dielectric layer comprises silicon oxide.

12. The method of claim 9 , further comprising:

forming a bonding layer on the first surface of the substrate;

bonding an other substrate to the bonding layer;

flipping the substrate on top of the other substrate; and

removing a portion of the substrate.

13. The method of claim 9 , wherein the forming the first dielectric barrier comprises:

depositing a blanket dielectric layer in the opening; and

etching a portion of the first blanket dielectric layer on the first S/D region.

14. The method of claim 9 , wherein the forming the first S/D contact comprises:

forming a silicide layer on the first S/D region; and

forming a metal contact on the silicide layer.

15. The method of claim 9 , wherein the portion of the first S/D region comprises an epitaxial stop layer and the portion of the second S/D region comprises an other epitaxial stop layer.

16. The method of claim 9 , wherein the first and the second dielectric barriers comprise silicon nitride.

17. An integrated circuit, comprising:

a stacked semiconductor device on a first surface of a substrate, wherein the stacked semiconductor device comprises:

a first fin structure comprising a first source/drain (S/D) region;

an isolation structure on the first fin structure; and

a second fin structure above the first fin structure and in contact with the isolation structure, wherein the second fin structure comprises a second S/D region; and

an S/D contact on a second surface of the substrate and connected to the first S/D region or the second S/D region, wherein the second surface is opposite to the first surface; and

a dielectric barrier surrounding the S/D contact, wherein the dielectric barrier comprises silicon nitride.

18. The integrated circuit of claim 17 , further comprising:

an other substrate; and

a bonding layer bonding the first surface of the substrate to the other substrate.

19. The integrated circuit of claim 17 , further comprising a dielectric layer around the S/D contact, wherein the dielectric layer comprises silicon oxide.

20. The integrated circuit of claim 17 , wherein the S/D contact comprises a silicide layer and a metal contact.