Semiconductor structure having sets of III-V compound layers and method of forming
A semiconductor structure includes a substrate. The semiconductor structure further includes a first III-V layer over the substrate, wherein the first III-V layer includes a first dopant type. The semiconductor structure further includes a second III-V layer over the first III-V layer, wherein the second III-V layer has a second dopant type opposite the first dopant type. The semiconductor structure further includes a third III-V layer over the second III-V layer, wherein the third III-V layer has the first dopant type. The semiconductor structure further includes a fourth III-V layer over the third III-V layer, the fourth III-V layer having the second dopant type. The semiconductor structure further includes an active layer over the fourth III-V layer. The semiconductor structure further includes a dielectric layer over the active layer.
1. A semiconductor structure comprising:
a substrate;
a first III-V layer over the substrate, wherein the first III-V layer includes a first dopant type, and the first III-V layer has a first width in a first direction parallel to a top surface of the substrate;
a second III-V layer over the first III-V layer, wherein the second III-V layer has a second dopant type opposite the first dopant type, and
a third III-V layer over the second III-V layer, wherein the third III-V layer has the first dopant type;
a fourth III-V layer over the third III-V layer, the fourth III-V layer having the second dopant type;
an active layer over the fourth III-V layer, wherein the active layer has a second width in the first direction, and the second width is less than the first width; and
a dielectric layer over the active layer.
2. The semiconductor structure of claim 1 , further comprising a channel layer between the fourth III-V layer and the active layer.
3. The semiconductor structure of claim 1 , wherein at least one of the first III-V layer, the second III-V layer, the third III-V layer or the fourth III-V layer comprises GaN.
4. The semiconductor structure of claim 1 , further comprising a nucleation layer between the substrate and the first III-V layer.
5. The semiconductor structure of claim 4 , wherein the nucleation layer comprises AlN.
6. The semiconductor structure of claim 4 , wherein the nucleation layer is configured to reduce lattice mismatch between the substrate and the first III-V layer.
7. The semiconductor structure of claim 1 , further comprising a gate electrode over the dielectric layer.
8. The semiconductor structure of claim 1 , wherein sidewalls of the active layer are aligned with sidewalls of the dielectric layer.
9. A method of forming a semiconductor structure, the method comprising:
depositing a first III-V layer having a first-type dopant over a substrate, wherein depositing the first III-V layer comprises depositing the first III-V layer having a first width in a first direction parallel to a top surface of the substrate;
depositing a plurality of pairs of layers over the first III-V layer until a predetermined number of pairs is deposited, wherein each pair of layers of the plurality of pairs of layers includes a lower III-V compound layer and an upper III-V compound layer, the lower III-V compound layer is undoped or has a second doping type, and the upper III-V compound layer has the first-type dopant;
forming a second III-V compound layer over an upper-most layer of the plurality of pairs of layers, wherein the second III-V compound layer is undoped;
forming an active layer over the second III-V compound layer, wherein forming the active layer comprises forming the active layer having a second width in the first direction, and the second width is less than the first width; and
depositing a dielectric layer over the active layer.
10. The method of claim 9 , further comprising depositing a nucleation layer over the substrate, wherein the nucleation layer is between the substrate and the first III-V layer.
11. The method of claim 10 , wherein depositing the nucleation layer comprises depositing AlN.
12. The method of claim 10 , wherein depositing the nucleation layer comprises reducing lattice mismatch between the substrate and the first III-V layer.
13. The method of claim 9 , further comprising depositing a transition layer over the substrate, wherein the transition layer is between the substrate and the first III-V layer.
14. The method of claim 13 , wherein depositing the transition layer comprises depositing a multilayer structure.
15. The method of claim 14 , wherein depositing the transition layer comprises depositing a graded layer, wherein a first composition of the transition layer closest to the substrate is different from a second composition of the transition layer closest to the first III-V layer.
16. A semiconductor structure, comprising:
a substrate;
a first III-V layer over the substrate, the first III-V layer having P-type doping;
a second III-V layer over the first III-V layer, wherein the second III-V layer is undoped;
a third III-V layer over the second III-V layer, wherein the third III-V layer is P-type doped;
a fourth III-V layer over the third III-V layer, the fourth III-V layer being undoped;
an active layer over the fourth III-V layer; and
a dielectric layer directly contacting the active layer, wherein an outermost sidewall of the dielectric layer is offset in a direction parallel to a top surface of the substrate with respect to an outermost sidewall of the first III-V layer.
17. The semiconductor structure of claim 16 , further comprising a nucleation layer between the first III-V layer and the substrate.
18. The semiconductor structure of claim 17 , wherein the nucleation layer comprises AlN.
19. The semiconductor structure of claim 16 , further comprising a gate electrode over the dielectric layer.
20. The semiconductor structure of claim 16 , further comprising multiple layers between the first III-V layer and the substrate, wherein each layer of the multiple layer comprises aluminum.