IP Library Granted Patent US 11,201,137
Granted Patent B2
US 11,201,137 · App. 17/013,292 · Granted Dec 14, 2021

Systems and methods for powering an integrated circuit having multiple interconnected die

Inventor: Jean-Philippe Fricker (Los Altos, CA)
Assignee: Cerebras Systems Inc.
H01L25/0655H01L23/32H01L23/367H01L23/473H01L23/49811H01L23/49827H01L24/48H01L2224/48137
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Quick Facts
Patent No.
US 11,201,137
App. No.
17/013,292
Granted
Dec 14, 2021
Kind
B2
Abstract

The power on wafer assembly can include: a compliant connector, an integrated circuit, a printed circuit board (PCB), a power component, and a set of compliant connectors. The power on wafer assembly can optionally include: a compression element, a cooling system, a set of mechanical clamping components, and a power source. However, the power on wafer assembly can additionally or alternately include any other suitable components.

Claims (47)

1. An assembly comprising:

a printed circuit board (PCB) defining a first surface of the PCB;

an integrated circuit having a first set of conductive pads arranged along a second surface of the integrated circuit opposing the first surface;

a power converter arranged between first surface and the second surface, the power converter electrically connected to each of the first set of conductive pads;

a compliant connector extending between the first surface and the power converter; and

a cold plate arranged between the power converter and the PCB, the cold plate thermally connected to the power converter, wherein:

the cold plate is thermally connected to the power converter at a first region on a broad face of the power converter, and

the compliant connector is electrically connected to the power converter at a second region on the broad face of the power converter, the second region separate and distinct from the first region.

2. The assembly of claim 1 , wherein the integrated circuit comprises a wafer-scale processor.

3. The assembly of claim 2 , wherein the wafer-scale processor comprises a plurality of die formed on a unitary wafer substrate.

4. The assembly of claim 1 , wherein the cold plate is mechanically biased away from the PCB.

5. The assembly of claim 1 , wherein the second region comprises a periphery of the broad face of the power converter.

6. The assembly of claim 1 , wherein the power converter is compressed between the first surface and a power consuming region of the second surface.

7. The assembly of claim 1 :

wherein the power converter comprises a second set of conducting pads;

wherein the PCB comprises a third set of conducting pads, wherein each conducting pad of the third set is aligned with a different conducting pad of the second set, wherein the compliant connector electrically connects each conducting pad from the third set with the respective conducting pad from the second set.

8. The assembly of claim 7 , wherein the compliant connector comprises a plurality of arcuate electrical pathways of varying radii between the PCB and the power converter.

9. The assembly of claim 1 , wherein the PCB comprises:

a first aperture aligned with a die of the integrated circuit; and

a second aperture aligned with a portion of the integrated circuit outside of a die region.

10. The assembly of claim 1 , wherein the power converter comprises a voltage regulator.

11. The assembly of claim 10 , further comprising a decoupling capacitor opposing the voltage regulator across a thickness of the PCB.

12. The assembly of claim 1 , wherein the power converter further comprises a current transformer and a driver.

13. The assembly of claim 1 , further comprising:

a power source opposing the power converter across a thickness of the PCB; and

an electrical connection extending through the thickness of the PCB that connects the power source to the compliant connector.

14. The assembly of claim 13 , wherein the electrical connection extends orthogonal to the first surface.

15. The assembly of claim 1 , further comprising a plurality of clamping components mechanically coupling the PCB to the integrated circuit and preloading the compliant connector.

16. The assembly of claim 1 , wherein the power converter is directly affixed to the second surface of the integrated circuit.

17. The assembly of claim 1 , wherein the integrated circuit further comprises:

a semiconductor substrate;

a plurality of die lithographically formed within the semiconductor substrate; and

a circuit layer formed at each of the plurality of die, the circuit layer comprising the first set of conductive pads and a plurality of inter-die connections that communicatively connect adjacent die of the plurality of die.

18. The assembly of claim 17 , wherein the power converter is directly connected to the circuitry layer of the integrated circuit at the first set of conductive pads.

19. An assembly comprising:

a printed circuit board (PCB) defining a first surface of the PCB;

an integrated circuit having a first set of conductive pads arranged along a second surface of the integrated circuit opposing the first surface;

a power converter arranged between first surface and the second surface, the power converter electrically connected to each of the first set of conductive pads, wherein the power converter comprises a current transformer and a driver; and

a compliant connector extending between the first surface and the power converter.

20. An assembly comprising:

a printed circuit board (PCB) defining a first surface of the PCB;

an integrated circuit having a first set of conductive pads arranged along a second surface of the integrated circuit opposing the first surface;

a power converter arranged between first surface and the second surface, the power converter electrically connected to each of the first set of conductive pads; and

a compliant connector extending between the first surface and the power converter,

wherein the PCB comprises:

a first aperture aligned with a die of the integrated circuit; and

a second aperture aligned with a portion of the integrated circuit outside of a die region.

Assignments (2)
SECURITY INTEREST Recorded Jun 18, 2026
From: CEREBRAS SYSTEMS INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS THE COLLATERAL AGENT
Reel/Frame 075845/0844 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2020
From: FRICKER, JEAN-PHILIPPE
To: CEREBRAS SYSTEMS INC.
Reel/Frame 053699/0697 →
Continuity (3)
Continuation 16810520 · Mar 5, 2020
Provisional Application 62813889 · Mar 5, 2019
Related Publication 20200402957A1 · Dec 24, 2020