3D semiconductor device and structure
A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and each include at least two side gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.
1. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer and first transistors,
wherein said first transistors each comprise a single crystal channel;
first metal layers interconnecting at least said first transistors; and
a second level comprising a second single crystal layer and second transistors,
wherein said second level overlays said first level,
wherein said second transistors are horizontally oriented and each comprise at least two side gates,
wherein said second level is bonded to said first level, and
wherein said bonded comprises oxide to oxide bonds.
2. The device according to claim 1 ,
wherein said first level comprises alignment marks, and
wherein said second transistors are aligned to said alignment marks.
3. The device according to claim 1 ,
wherein said second transistors each comprise at least three side-gates.
4. The device according to claim 1 ,
wherein at least one of said second transistors is an N-type transistor and at least one of said second transistors is a P-type transistor.
5. The device according to claim 1 ,
wherein said first level comprises third transistors and fourth transistors,
wherein said fourth transistors are overlying said third transistors, and
wherein said third transistors and said fourth transistors are self-aligned, being processed following the same lithography step.
6. The device according to claim 1 ,
wherein said bonded comprises metal to metal bonds.
7. The device according to claim 1 ,
wherein said first level comprises a memory array, and
wherein said second level comprises control circuits for said memory array.
8. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer and alignment marks;
first transistors overlaying said first single crystal layer;
second transistors overlaying said first transistors; and
a second level comprising a second single crystal layer,
wherein said second level overlays said second transistors,
wherein said first transistors and said second transistors are self-aligned, being processed following the same lithography step,
wherein said second level comprises third transistors, and
wherein said third transistors are aligned to said alignment marks.
9. The device according to claim 8 ,
wherein each of said second transistors comprise a source, a channel, and a drain, and
wherein said source, said channel, and said drain have a similar doping type.
10. The device according to claim 8 ,
wherein said second transistors each comprise a polysilicon channel.
11. The device according to claim 8 ,
wherein each of said third transistors are horizontally oriented and each comprise at least two side gates.
12. The device according to claim 8 ,
wherein said second level is bonded to said first level, and
wherein said bonded comprises oxide to oxide bonds.
13. The device according to claim 8 ,
wherein said second level is bonded to said first level, and
wherein said bonded comprises metal to metal bonds.
14. The device according to claim 8 ,
wherein said device comprises an array of memory cells,
wherein a plurality of said memory cells comprise at least one of said second transistors, and
wherein said second level comprises a periphery circuit to control said array of memory cells.
15. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer and first transistors,
wherein said first transistors each comprise a single crystal channel;
first metal layers interconnecting at least said first transistors;
alignment marks,
wherein said first level comprises said alignment marks; and
a second level comprising a second single crystal layer and second transistors,
wherein said second level overlays said first level,
wherein said second transistors are horizontally oriented and each comprise at least two side gates,
wherein said second level is bonded to said first level,
wherein said bonded comprises oxide to oxide bonds, and
wherein said second transistors are aligned to said alignment marks.
16. The device according to claim 15 ,
wherein said second transistors each comprise at least three side gates.
17. The device according to claim 15 ,
wherein at least one of said second transistors is an N-type transistor and at least one of said second transistors is a P-type transistor.
18. The device according to claim 15 ,
wherein said first level comprises third transistors and fourth transistors,
wherein said fourth transistors are overlying said third transistors, and
wherein said third transistors and said fourth transistors are self-aligned, being processed following the same lithography step.
19. The device according to claim 15 ,
wherein said bonded comprises metal to metal bonds.
20. The device according to claim 15 ,
wherein said first level comprises a memory array, and
wherein said second level comprises control circuits for said memory array.