3D semiconductor device and structure
A 3D semiconductor device, the device including: a first die including first transistors and first interconnect; and a second die including second transistors and second interconnect, where the first die is overlaid by the second die, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is pretested, where the second die includes an array of memory cells, where the first die includes control logic to control reads and writes to the array of memory cells, where the second die is bonded to the first die, and where the bonded includes hybrid bonding.
1. A 3D semiconductor device, the device comprising:
a first die comprising first transistors and a first interconnect; and
a second die comprising second transistors and a second interconnect,
wherein said first die is overlaid by said second die,
wherein said second die is bonded to said first die,
wherein said bonded comprises hybrid bonding,
wherein said second die comprises at least two alignment marks positioned close to a die edge of said second die,
wherein second die comprises an array of memory cells, and
wherein said first die comprises a control logic to control reads and writes to said array of memory cells.
2. The 3D semiconductor device according to claim 1 ,
wherein said first die has a first die area and said second die has a second die area,
wherein said first die area is at least 10% larger than said second die area.
3. The 3D semiconductor device according to claim 1 ,
wherein said first die is sourced from a first wafer with a diameter greater than 280 mm and said second die is sourced from a second wafer with a diameter less than 240 mm.
4. The 3D semiconductor device according to claim 1 ,
wherein said second die is aligned to said first die with less than 800 nm alignment error.
5. The 3D semiconductor device according to claim 1 , further comprising:
a through second die via having a diameter of less than 400 nm.
6. The 3D semiconductor device according to claim 1 ,
wherein said second die is pretested.
7. A 3D semiconductor device, the device comprising:
a first die comprising first transistors and a first interconnect; and
a second die comprising second transistors and a second interconnect,
wherein said first die is overlaid by said second die,
wherein said second die is bonded to said first die,
wherein said bonded comprises hybrid bonding,
wherein said second die comprises at least two alignment marks positioned close to a die edge of said second die,
wherein second die comprises an array of memory cells,
wherein said first die comprises a control logic to control reads and writes to said array of memory cells, and
wherein said control logic comprises memory decoders.
8. The 3D semiconductor device according to claim 7 ,
wherein said first die is sourced from a first wafer with a first diameter greater than 280 mm and said second die is sourced from a second wafer with a second diameter less than 240 mm.
9. The 3D semiconductor device according to claim 7 ,
wherein said first die has a first die area and said second die has a second die area, and
wherein said first die area is at least 10% larger than said second die area.
10. The 3D semiconductor device according to claim 7 , further comprising:
a third die directly overlaying said first die,
wherein said third die is pretested.
11. The 3D semiconductor device according to claim 7 ,
wherein said second die is aligned to said first die with less than 800 nm alignment error.
12. The 3D semiconductor device according to claim 7 , further comprising:
a through second die via having a diameter of less than 400 nm.
13. A 3D semiconductor device, the device comprising:
a first die comprising first transistors and a first interconnect; and
a second die comprising second transistors and a second interconnect,
wherein said first die is overlaid by said second die,
wherein said first die has a first die area and said second die has a second die area,
wherein said first die area is at least 10% larger than said second die area,
wherein said second die is pretested,
wherein said second die comprises an array of memory cells,
wherein said first die comprises a control logic to control reads and writes to said array of memory cells,
wherein said second die is bonded to said first die,
wherein said bonded comprises hybrid bonding, and
wherein said second die comprises at least two alignment marks positioned close to a die edge of said second die.
14. The 3D semiconductor device according to claim 13 , further comprising:
a third die directly overlaying said first die,
wherein said third die is pretested.
15. The 3D semiconductor device according to claim 13 ,
wherein said second die is aligned to said first die with less than 800 nm alignment error.
16. The 3D semiconductor device according to claim 13 , further comprising:
a through second die via having a diameter of less than 400 nm.
17. The 3D semiconductor device according to claim 1 ,
wherein said control logic comprises memory decoders.