Bi-layer alloy liner for interconnect metallization and methods of forming the same

1. A method of forming a semiconductor device, comprising:

forming an opening in a dielectric layer;

forming a barrier layer in the opening;

forming a combined liner layer over the barrier layer, the forming the combined liner layer comprising:

forming a first liner layer over the barrier layer, the first liner layer comprising ruthenium, the barrier layer being free of cobalt;

after forming the first liner layer, forming a second liner layer over the first liner layer, the second liner layer comprising cobalt; and

after forming the second liner layer, performing a hydrogen treatment to intermix the first liner layer and the second liner layer to form the combined liner layer, wherein the hydrogen treatment results in an exposed surface of the combined liner layer comprising ruthenium;

forming a conductive material layer over the combined liner layer, the conductive material layer comprising copper; and

performing a thermal process to reflow the conductive material layer.

2. The method of claim 1 , wherein performing the hydrogen treatment to form the combined liner layer further comprises performing a hydrogen plasma treatment.

3. The method of claim 2 , wherein during the hydrogen plasma treatment, ruthenium in the first liner layer intermixes with cobalt in the second liner layer resulting in the exposed surface of the combined liner layer comprising 5-20% ruthenium.

4. The method of claim 1 further comprising forming a capping layer over the conductive material layer, the capping layer comprising cobalt.

5. The method of claim 4 , wherein the forming the capping layer comprises:

depositing cobalt over the conductive material layer, the combined liner layer, the barrier layer, and the dielectric layer; and

etching the cobalt to expose a surface of the dielectric layer.

6. The method of claim 1 , wherein the barrier layer is physically and electrically coupled to a contact plug.

7. The method of claim 6 further comprising forming a metallization feature over and electrically coupled to the conductive material layer.

8. The method of claim 7 further comprising after forming the conductive material layer, planarizing the conductive material layer, a top surface of the conductive material layer being level with a top surface of the combined liner layer and a top surface of the dielectric layer.

9. A method of forming a semiconductor device, comprising:

depositing a dielectric layer over a substrate;

patterning the dielectric layer to form an opening, the opening comprising sidewalls and a bottom surface;

depositing a barrier layer over the dielectric layer and in the opening;

depositing a ruthenium layer over an exposed surface of the barrier layer;

depositing a cobalt layer over an exposed surface of the ruthenium layer;

performing a hydrogen plasma treatment on an exposed surface of the cobalt layer to result in an intermixed binary layer comprising ruthenium and cobalt; and

depositing a first copper layer over an exposed surface of the intermixed binary layer, the exposed surface of the intermixed binary layer comprising ruthenium.

10. The method of claim 9 , wherein the ruthenium layer has a first thickness greater than or equal to about 5 Å.

11. The method of claim 10 , wherein the cobalt layer has a second thickness greater than or equal to about 10 Å, a sum of the first thickness and the second thickness being between about 20 Å and about 40 Å.

12. The method of claim 9 , wherein after the hydrogen plasma treatment a surface of the intermixed binary layer opposite of the substrate comprises between about 5% and about 20% ruthenium.

13. The method of claim 9 further comprising performing a first thermal process to reflow the first copper layer.

14. The method of claim 13 further comprising:

depositing a second copper layer over the first copper layer; and

performing a second thermal process to reflow the first copper layer and the second copper layer.

15. The method of claim 9 further comprising forming a capping layer over the first copper layer, the capping layer comprising cobalt.

16. The method of claim 15 further comprising performing an electromigration test to measure electromigration of cobalt atoms from the capping layer to the intermixed binary layer.

17. A method of forming a semiconductor device, comprising:

forming a recess in a first dielectric layer;

depositing a first conductive layer in the recess;

depositing a second conductive layer over the first conductive layer;

depositing a third conductive layer over the second conductive layer;

performing a plasma treatment to form an alloy layer, the alloy layer comprising metals in the second conductive layer and the third conductive layer, wherein the plasma treatment is free of the metals in the second conductive layer and the third conductive layer;

depositing a fourth conductive layer over the alloy layer; and

planarizing the first conductive layer, the alloy layer, and the fourth conductive layer.

18. The method of claim 17 , wherein the depositing the fourth conductive layer comprises:

depositing a first copper layer;

performing a first thermal treatment;

depositing a second copper layer; and

performing a second thermal treatment.

19. The method of claim 18 , wherein the first thermal treatment reflows the first copper layer, and wherein the second thermal treatment reflows the second copper layer.

20. The method of claim 17 , wherein the second conductive layer comprises ruthenium, and wherein the third conductive layer comprises cobalt.