Bi-layer alloy liner for interconnect metallization and methods of forming the same
A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.
1. A method of forming a semiconductor device, comprising:
forming an opening in a dielectric layer;
forming a metal nitride layer in the opening;
forming a combined liner layer over the metal nitride layer, the forming the combined liner layer comprising:
forming a first liner layer over the metal nitride layer, the first liner layer being a first metal;
after forming the first liner layer, forming a second liner layer over the first liner layer, the second liner layer being a second metal, the second metal being different from the first metal; and
after forming the second liner layer, performing a treatment to intermix the first liner layer and the second liner layer to form the combined liner layer, wherein the treatment results in an exposed surface of the combined liner layer comprising the first metal; and
forming a conductive material layer over the combined liner layer.
2. The method of claim 1 , wherein the conductive material layer is a third metal, the third metal being different from the first metal and the second metal.
3. The method of claim 2 , further comprising forming a conductive capping layer over the conductive material layer.
4. The method of claim 3 , wherein the conductive capping layer is the second metal.
5. The method of claim 1 , wherein the treatment to intermix the first liner layer and the second liner layer comprises a hydrogen plasma treatment.
6. The method of claim 1 , wherein the treatment to intermix the first liner layer and the second liner layer is free of the first metal and the second metal.
7. The method of claim 1 , wherein the first metal is ruthenium, and wherein the second metal is cobalt.
8. The method of claim 1 , wherein forming the conductive material layer comprises:
depositing a first metal layer;
performing a thermal treatment to reflow the first metal layer; and
after performing the thermal treatment, depositing a second metal layer.
9. A method of forming a semiconductor device, comprising:
depositing a dielectric layer over a substrate;
patterning the dielectric layer to form an opening, the opening comprising sidewalls and a bottom surface;
depositing a barrier layer over the dielectric layer and in the opening, the barrier layer comprising a first metal nitride;
depositing a second metal layer over a first exposed surface of the barrier layer, a first metal of the first metal nitride being different from a second metal of the second metal layer;
depositing a third metal layer over a second exposed surface of the second metal layer, a third metal of the third metal layer being different from the first metal and the second metal;
performing a treatment on a third exposed surface of the third metal layer, after performing the treatment, the third exposed surface comprising the second metal; and
after performing the treatment, depositing a fourth metal layer over the third exposed surface, a fourth metal of the fourth metal layer being different from the first metal, the second metal, and the third metal.
10. The method of claim 9 , wherein after performing the treatment, the third exposed surface comprises between 5% and 20% of the second metal.
11. The method of claim 9 , wherein the first metal is titanium or tantalum.
12. The method of claim 9 , wherein the second metal is ruthenium, and wherein the third metal is cobalt.
13. The method of claim 9 , wherein a thickness of the second metal layer is between 5 Å and 6 Å, and wherein a thickness of the third metal layer is between 10 Å and 25 Å.
14. The method of claim 9 , further comprising forming a cobalt capping layer over the fourth metal layer.
15. A method of forming a semiconductor device, comprising:
forming a recess in a first dielectric layer;
depositing a first conductive layer in the recess;
depositing a second conductive layer over the first conductive layer;
depositing a third conductive layer over the second conductive layer;
performing a treatment to form an alloy layer, an exposed surface of the alloy layer comprising a metal from the second conductive layer, wherein the treatment is free of the metals in the second conductive layer and the third conductive layer;
depositing a fourth conductive layer over the alloy layer;
planarizing the first conductive layer, the alloy layer, and the fourth conductive layer; and
forming a capping layer over the fourth conductive layer, the capping layer comprising a same metal as the third conductive layer.
16. The method of claim 15 , wherein the treatment comprises a hydrogen soak treatment at a pressure between 10 Torr and 50 Torr.
17. The method of claim 15 , wherein the treatment comprises a hydrogen plasma treatment at a pressure between 1 Torr and 15 Torr.
18. The method of claim 15 , wherein the exposed surface comprises 5% to 20% of the metal from the second conductive layer.
19. The method of claim 15 , wherein the second conductive layer comprises ruthenium, and wherein the third conductive layer comprises cobalt.
20. The method of claim 19 , wherein the first conductive layer is a metal nitride.