Capacitance reduction for backside power rail device
The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.
1. A method, comprising:
forming a fin structure on a first side of a substrate;
forming a source/drain (S/D) region adjacent to the fin structure;
forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region;
forming a capping structure on the first S/D contact structure;
removing a portion of the first S/D contact structure through the capping structure to form an air gap; and
forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region, wherein the second side is opposite to the first side.
2. The method of claim 1 , wherein the first S/D contact structure comprises a metal contact, and wherein the removing the portion of the first S/D contact structure comprises:
forming an opening in the capping structure;
removing the metal contact through the opening to form the air gap; and
forming a seal structure in the opening to seal the air gap.
3. The method of claim 2 , wherein the forming the seal structure comprises depositing a dielectric material in the opening and in the air gap.
4. The method of claim 1 , wherein the first S/D contact structure comprises a metal contact and a silicide layer, and wherein the removing the portion of the S/D contact structure comprises:
forming an opening in the capping structure;
removing the metal contact and the silicide layer through the opening to form the air gap; and
forming a seal structure in the opening to seal the airgap.
5. The method of claim 1 , wherein the forming the S/D region comprises:
forming a first portion of the S/D region in the substrate; and
forming a second portion of the S/D region in contact with the fin structure, wherein the first S/D contact structure is in contact with the second portion.
6. The method of claim 1 , wherein the forming the second S/D contact structure comprises:
replacing the substrate with a dielectric layer;
removing a portion of the S/D region on the second side of the substrate; and
forming a silicide layer in contact with the S/D region on the second side of the substrate.
7. The method of claim 1 , further comprising forming an interconnect structure in contact with the second S/D contact structure.
8. A method, comprising:
forming a fin structure on a first side of a substrate;
forming first and second source/drain (S/D) regions adjacent to opposite ends of the fin structure;
forming a first S/D contact structure in contact with the first S/D region and a second S/D contact structure in contact with the second S/D region on the first side of the substrate;
forming a first capping structure on the first S/D contact structure and a second capping structure on the second S/D contact structure;
removing a portion of the second contact structure through the second capping structure to form an air gap; and
forming a third contact structure on a second side of the substrate and in contact with the second S/D region, wherein the second side is opposite to the first side.
9. The method of claim 8 , wherein the second S/D contact structure comprises a metal contact, and wherein the removing the portion of the second S/D contact structure comprises:
forming an opening in the second capping structure;
removing the metal contact through the opening to form the air gap; and
forming a seal structure in the opening to seal the air gap.
10. The method of claim 9 , wherein the forming the seal structure comprises depositing a dielectric material in the opening and in the air gap.
11. The method of claim 8 , wherein the second S/D contact structure comprises a metal contact and a silicide layer, and wherein the removing the portion of the second S/D contact structure comprises:
forming an opening in the second capping structure;
removing the metal contact and the silicide layer through the opening to form the air gap; and
forming a seal structure in the opening to seal the air gap.
12. The method of claim 8 , wherein the forming the second S/D region comprises:
forming a first portion of the second S/D region in the substrate; and
forming a second portion of the second S/D region in contact with the fin structure, wherein the second S/D contact structure is in contact with the second portion.
13. The method of claim 8 , wherein the forming the third contact structure comprises:
replacing the substrate with a dielectric layer;
removing a portion of the second SID region on the second side of the substrate; and
forming a silicide layer in contact with the second S/D region on the second side of the substrate.
14. The method of claim 8 , further comprising:
forming a first interconnect structure on the first side in contact with the first S/D contact structure; and
forming a second interconnect structure on the second side in contact with the third contact structure.
15. A semiconductor device, comprising:
a fin structure on a first side of a substrate;
first and second source/drain (S/D) regions adjacent to opposite ends of the fin structure;
a first S/D contact structure in contact with the first S/D region;
a first capping structure on the first contact structure;
a second capping structure over the second S/D region;
an air gap between the second capping structure and the second S/D region, wherein the air gap is in contact with the second capping structure; and
a second S/D contact structure in contact with the second S/D region on a second side of the substrate, wherein the second side is opposite to the first side.
16. The semiconductor device of claim 15 , further comprising a silicide layer on the second S/D region in the air gap.
17. The semiconductor device of claim 15 , further comprising a seal structure in the second capping structure to seal the air gap, wherein the seal structure comprises a dielectric material.
18. The semiconductor device of claim 17 , further comprising a layer of the dielectric material in the air gap.
19. The semiconductor device of claim 15 , further comprising:
a first interconnect structure on the first side of the substrate and in contact with the first S/D contact structure; and
a second interconnect structure on the second side of the substrate and in contact with the second contact structure.
20. The semiconductor device of claim 15 , wherein the first contact structure comprises a metal contact and a first silicide layer, and wherein the second contact structure comprises a second silicide layer.