Manufacturing method of a semiconductor device and method for creating a layout thereof
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
1. A semiconductor device comprising:
a semiconductor substrate extending in a first direction, a second direction, and a third direction, the first to third directions crossing one another, the semiconductor substrate having a front surface at a first side in the third direction and a rear surface at a second side in the third direction, the first surface having patterns having different heights in the third direction, the rear surface having a planar shape extending in the first direction and the second direction;
a first conductive line formed on the front surface of the semiconductor substrate and extending in the first direction;
a second conductive line formed on the front surface of the semiconductor substrate and extending in the first direction, the first conductive line and the second conductive line being provided in an imaginary plane crossing the third direction;
a dummy area formed on the front surface of the semiconductor substrate between the first conductive line and the second conductive line, and being electrically isolated from the first conductive line and the second conductive line,
the dummy area including first to fourth conductive patterns being electrically isolated from one another,
the first conductive pattern having an elongated shape in a fourth direction when viewed in the third direction, the fourth direction being different from the first direction,
the first and second conductive patterns being arranged in this order along the fourth direction, a dimension of the second conductive pattern in the fourth direction is smaller than a dimension of the first conductive pattern in the fourth direction when viewed in the third direction, and
the third, first and fourth conductive patterns being in this order along a fifth direction, the fifth direction being different from the second direction, a dimension of the third conductive pattern in the fourth direction is smaller than the dimension of the first conductive pattern the fourth direction when viewed in the third direction, a dimension of the fourth conductive pattern in the fourth direction is smaller than the dimension of the first conductive pattern in the fourth direction when viewed in the third direction.
2. The semiconductor device according to claim 1 , wherein
a shape of third conductive pattern is geometrically similar to a shape of second conductive pattern when viewed in the third direction, and
a shape of fourth conductive pattern is geometrically similar to the shape of second conductive pattern when viewed in the third direction.
3. The semiconductor device according to claim 2 , wherein
the dimension of the third conductive pattern in the fourth direction is the same with the dimension of the second conductive pattern in the fourth direction when viewed in the third direction, and
the dimension of the fourth conductive pattern in the fourth direction is the same with the dimension of the second conductive pattern in the fourth direction when viewed in the third direction.
4. The semiconductor device according to claim 3 , wherein
the dimension of the third conductive pattern in the first direction is smaller than the dimension of the first conductive pa tem in the fourth direction when viewed in the third direction, and
the dimension of the fourth conductive pattern in the first direction is smaller than the dimension of the first conductive pattern in the fourth direction when viewed in the third direction.
5. The semiconductor device according to claim 1 , wherein the first conductive line and the conductive second line are functioning lines.
6. The semiconductor device according to claim 1 , wherein
the dummy area further includes fifth and sixth conductive patterns, the first to sixth conductive patterns being electrically isolated from one another.
7. The semiconductor device according to claim 1 , wherein the first to fourth conductive patterns have shapes based on a sidewall transfer processing.
8. The semiconductor device according to claim 1 , wherein the first to fourth conductive patterns include a detailed pattern exceeding resolution limits of optical lithography.
9. The semiconductor device according to claim 1 , wherein the semiconductor device is a NAND flash memory device.
10. The semiconductor device according to claim 1 , further comprising:
a first functioning area extending in the first direction at one side of the dummy area in the second direction, the first conductive line being provided in plurality in the first functioning area;
a pattern density of the plurality of first conductive lines in the first functioning area being larger than a pattern density of the first to fourth conductive patterns.
11. The semiconductor device according to claim 10 , further comprising:
a second functioning area extending in the first direction at a second side of the dummy area in the second direction, the second conductive line being provided in plurality in the second functioning area;
a pattern density of the plurality of second conductive lines in the first functioning area being larger than the pattern density of the first to fourth conductive patterns.
12. The semiconductor device according to claim 11 , wherein the pattern density of the plurality of first conductive lines in the first functioning area is the same as the pattern density of the plurality of second conductive lines in the second functioning area.
13. The semiconductor device according to claim 11 , wherein a spatial density in the first functioning area is the same as a spatial density in the second functioning area.
14. The semiconductor device according to claim 11 , further comprising:
a connecting portion electrically connecting one of the first conductive lines adjacent to the dummy area and one of the second conductive lines adjacent to the dummy area,
wherein at least part of the first to fourth conductive patterns are arranged adjacent to the connecting portion.
15. The semiconductor device according to claim 1 , wherein the dummy area includes a plurality of insulating curved lines.
16. The semiconductor device according to claim 15 , wherein
the insulating curved lines include:
a first insulating curved line extending between the first and second conductive pattern,
a second insulating curved line extending between the first and third conductive pattern, and
a third insulating curved line extending between the first and fourth conductive pattern.
17. The semiconductor device according to claim 15 , wherein
each of the first to fourth conductive patterns has at least one curved corner, when viewed in the third direction.