Memory cell and methods thereof

1. A memory cell comprising:

a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal to control the memory cell;

a first memory element and a second memory element;

the first memory element comprising a first capacitive memory structure electrically connected to the first terminal and a first field-effect transistor structure coupled to the first capacitive memory structure and electrically connected to the third terminal and the fourth terminal;

the second memory element comprising a second capacitive memory structure electrically connected to the second terminal and a second field-effect transistor structure coupled to the second capacitive memory structure and electrically connected to the third terminal and the fifth terminal.

2. Memory cell according to claim 1 , wherein the first capacitive memory structure and the first field-effect transistor structure are coupled with one another to form a capacitive voltage divider; and/or wherein the second capacitive memory structure and the second field-effect transistor structure are coupled with one another to form a capacitive voltage divider.

3. Memory cell according to claim 1 , wherein a source region of the first field-effect transistor structure is coupled to the third terminal.

4. Memory cell according to claim 1 , wherein a source region of the second field-effect transistor structure is coupled to the third terminal.

5. Memory cell according to claim 1 , wherein a drain region of the first field-effect transistor structure is coupled to the fourth terminal.

6. Memory cell according to claim 1 , wherein a drain region of the second field-effect transistor structure is coupled to the fifth terminal.

7. Memory cell according to claim 1 , further comprising: a substrate comprising a semiconductor region of a same doping type, wherein the first memory element and the second memory element are embedded in the semiconductor region.

8. Memory cell according to claim 1 , further comprising:

a read-out circuit configured to sense a voltage at the fourth terminal and/or at the fifth terminal and/or to provide an output signal (Q) representing a memory state of the memory cell based on the sensed voltage at the fourth terminal or at the fifth terminal.

9. Memory cell according to claim 1 , further comprising one or more control circuits configured to operate the first memory element and the second memory element differentially; and/or the first memory element and the second memory element according to a control schema.

10. Memory cell according to claim 9 , wherein, in a first phase of the control schema, a first voltage at the first terminal is more than a second voltage at the second terminal and is more than a third voltage at the third terminal.

11. Memory cell according to claim 10 , wherein, in a second phase of the control schema, a second voltage at the second terminal is less than the first voltage at the first terminal and is less than the third voltage at the third terminal.

12. Memory cell according to claim 11 , wherein the first voltage at the first terminal is increased before the first phase and decreased after the second phase.

13. Memory cell according to claim 9 , wherein at least one of the one or more control circuits includes a first circuit branch coupled to the first memory element and a second circuit branch coupled to the second memory element; wherein the first circuit branch and the second circuit branch are coupled parallel to each other.

14. Memory cell according to claim 9 , wherein at least one of the one or more control circuits comprises a level shifter.

15. Memory cell according to claim 9 , wherein at least one of the one or more control circuits comprises a cascode circuit.

16. Memory cell according to claim 9 , wherein at least one of the one or more control circuits comprises a latch structure.

17. Memory cell according to claim 1 , wherein the first capacitive memory structure and/or the second capacitive memory structure comprise one or more remanent-polarizable layers.

18. Memory cell according to claim 17 , wherein a material of the one or more remanent-polarizable layers comprises at least one of:

hafnium oxide,

zirconium oxide, or

a mixture of hafnium oxide and zirconium oxide.

19. A memory cell comprising:

a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal to control the memory cell;

a first ferroelectric memory element and a second ferroelectric memory element,

the first ferroelectric memory element comprising a first capacitive memory structure electrically connected to the first terminal and a first field-effect transistor structure coupled to the first capacitive memory structure and electrically connected to the third terminal and the fourth terminal;

the second ferroelectric memory element comprising a second capacitive memory structure electrically connected to the second terminal and a second field-effect transistor structure coupled to the second capacitive memory structure and electrically connected to the third terminal and the fifth terminal.

20. A method of forming a memory cell, the method comprising:

forming a first memory element and a second memory element; and

forming a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal to control the memory cell;

the first memory element comprising a first capacitive memory structure electrically connected to the first terminal and a first field-effect transistor structure coupled to the first capacitive memory structure and electrically connected to the third terminal and the fourth terminal;

the second memory element comprising a second capacitive memory structure electrically connected to the second terminal and a second field-effect transistor structure coupled to the second capacitive memory structure and electrically connected to the third terminal and the fifth terminal.