Memory cell with access device and memory capacitor structures
A memory cell arrangement is provided that may include: one or more memory cells, each memory cell of the one or more memory cells including: a field-effect transistor structure; a plurality of first control nodes; a plurality of first capacitor structures, a second control node; and a second capacitor structure including a first electrode connected to the second control node and a second electrode connected to a gate region of the field-effect transistor. Each of the plurality of first capacitor structures includes a first electrode connected to a corresponding first control node of the plurality of first control nodes, a second electrode connected to the gate region of the field-effect transistor structure, and a spontaneous-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure.
1. A memory cell comprising:
an access device;
a plurality of word-line nodes;
a plurality of memory capacitor structures, each of the plurality of memory capacitor structures comprising a first electrode connected to a corresponding word-line node of the plurality of word-line nodes, a second electrode connected to the access device, and a spontaneous-polarizable region disposed between the first electrode and the second electrode.
2. The memory cell of claim 1 , wherein the access device comprises an n-type field-effect transistor (FET), a p-type FET, an n-type-based transmission gate, or a p-type-based transmission gate.
3. The memory cell of claim 1 , wherein the access device comprises a field-effect transistor structure and the second electrode is connected to the field-effect transistor structure.
4. The memory cell of claim 1 ,
wherein each memory capacitor structure of the plurality of memory capacitor structures is configured to reside in one of at least two memory states.
5. The memory cell of claim 1 , wherein the access device comprises a field-effect transistor structure, the memory cell further comprising:
a bit-line coupled to a first source/drain region and/or second source/drain region of the field-effect transistor structure.
6. The memory cell of claim 5 ,
wherein the plurality of word-line nodes allow for an individual operation of each of the plurality of memory capacitor structures via the access device.
7. The memory cell of claim 1 ,
wherein the memory cell is configured to allow for an individual operation of a plurality of sub memory cells, each sub memory cell of the plurality of sub memory cells is provided by one of the plurality of memory capacitor structures and the access device and wherein each sub memory cell is configured to store information via writing the sub memory cell into one of at least two memory states.
8. The memory cell of claim 1 ,
wherein the first electrode of each of the plurality of memory capacitor structures is a shared first electrode.
9. The memory cell of claim 8 ,
wherein the second electrode of each of the plurality of memory capacitor structures is provided by a corresponding electrode layer electrode layer of a plurality of electrode layers;
wherein the shared first electrode has a pillar shape and extends through the plurality of electrode layers.
10. A memory cell arrangement, comprising:
a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
an access device;
a plurality of control nodes;
a plurality of memory capacitor structures, each of the plurality of memory capacitor structures comprising a first electrode connected to a corresponding control node of the plurality of control nodes, a second electrode connected to the access device, and a spontaneous-polarizable region disposed between the first electrode and the second electrode.
11. The memory cell arrangement of claim 10 ,
wherein each memory capacitor structure of the plurality of memory capacitor structures is configured to reside in one of at least two memory states.
12. The memory cell arrangement of claim 10 , wherein the access device comprises a field-effect transistor structure and each memory cell of the plurality of memory cells further comprises:
a further control node coupled to a first source/drain region and/or second source/drain region of the field-effect transistor structure; and
wherein the plurality of control nodes and the further control node are configured to allow for an operation a respective memory cell of the plurality of memory cells.
13. The memory cell arrangement of claim 12 , further comprising:
a bit-line and/or a source line to address a subset of memory cells of the plurality of memory cells, wherein the further control node of each memory cell of the subset of memory cells is connected to the bit-line and/or the source-line; and
a plurality of control-lines to address the subset of memory cells, wherein the plurality of control-lines are connected to the plurality of control nodes of each memory cell of the subset of memory cells.
14. The memory cell arrangement of claim 10 , further comprising:
a control circuit configured to write a selected memory capacitor structure of a selected memory cell of the plurality of memory cells; wherein writing the selected memory capacitor structure comprises:
providing a write-voltage to a control-line connected to a control node of the plurality of control nodes that corresponds to the selected memory capacitor structure of the selected memory cell.
15. The memory cell arrangement of claim 14 , wherein the access device comprises a field-effect transistor structure and each memory cell of the plurality of memory cells further comprises:
a further control node coupled to a first region and/or second region of the field-effect transistor structure;
wherein writing the selected memory capacitor structure of the selected memory cell further comprises:
providing a control-voltage to a bit-line and/or a source-line connected to the further control node of the selected memory cell.
16. The memory cell arrangement of claim 14 ,
wherein the control circuit is further configured to prevent a writing of non-selected memory capacitor structures of the selected memory cell during writing the selected memory capacitor structure of the selected memory cell, wherein prevent the writing of the non-selected memory capacitor structures comprises:
providing a first inhibit-voltage to each control-line that is connected to a control node of the plurality of control nodes associated with the non-selected memory capacitor structures of the selected memory cell.
17. The memory cell arrangement of claim 14 ,
wherein the control circuit is further configured to prevent a writing of the plurality of memory capacitor structures of a non-selected memory cell of the plurality of memory cells during writing the selected memory capacitor structure of the selected memory cell, wherein prevent the writing of the plurality of memory capacitor structures of the non-selected memory cell comprises:
providing an inhibit-voltage to a plurality of control-lines connected to the plurality of control nodes of the non-selected memory cell, wherein a voltage value of the inhibit-voltage value is different from a voltage value of the write-voltage.
18. The memory cell arrangement of claim 10 , further comprising:
a control circuit configured to read a selected memory capacitor structure of a selected memory cell of the plurality of memory cells; wherein reading the selected memory capacitor structure comprises:
providing a read-voltage to a control-line connected to the control node of the selected memory capacitor structure of the selected memory cell.
19. The memory cell arrangement of claim 18 , wherein the access device comprises a field-effect transistor structure and each memory cell of the plurality of memory cells further comprises:
a further control node coupled to a first source/drain region and/or second source/drain region of the field-effect transistor structure;
wherein reading the selected memory capacitor structure of the selected memory cell further comprises:
providing a control-voltage to a bit-line and/or a source-line connected to the further control node of the selected memory cell.
20. The memory cell arrangement of claim 10 ,
wherein, for each memory cell of the plurality of memory cells, the first electrode of each of the plurality of memory capacitor structures is a shared first electrode; and
wherein the second electrode of each of the plurality of memory capacitor structures is provided by a corresponding electrode layer electrode layer of a plurality of electrode layers; and
wherein the shared first electrode has a pillar shape and extends through the plurality of electrode layers.