Memory cell, memory cell arrangement, and methods thereof
Various aspects relate to a memory cell including: a field-effect transistor structure, the field-effect transistor structure including a gate structure to control a current flow in a channel, the gate structure including a gate isolation and a floating gate, wherein at least a part of the gate structure extends from a surface of a semiconductor layer into the semiconductor layer; and a capacitive memory structure, the capacitive memory structure including at least two electrodes and a spontaneously polarizable layer disposed between the at least two electrodes, wherein one of the at least two electrodes is in direct physical contact with the floating gate of the field-effect transistor structure, and wherein the spontaneously polarizable layer is disposed over the surface of the semiconductor layer.
1 . A memory cell comprising:
a semiconductor layer;
a recess disposed in the semiconductor layer;
a first source/drain region and a second source/drain region disposed in the semiconductor layer adjacent to the recess;
a floating gate disposed fully in the recess and a gate isolation disposed at least partially in the recess between the floating gate and the semiconductor layer;
a first electrode disposed over the floating gate and in electrical contact with the floating gate; wherein the first electrode is at least partially disposed in the recess;
a spontaneously polarizable layer disposed over the first electrode and a second electrode disposed over the spontaneously polarizable layer.
2 . The memory cell of claim 1 ,
wherein the spontaneously polarizable layer, the first electrode, and the second electrode form a capacitive memory structure of the memory cell; and
wherein the semiconductor layer, the first source/drain region, the second source/drain region, the floating gate, and the gate isolation form a field-effect transistor structure of the memory cell.
3 . The memory cell of claim 2 ,
wherein the memory cell is configured such that a change of a polarization state of the spontaneously polarizable layer modifies a threshold value of the field-effect transistor structure of the memory cell.
4 . The memory cell of claim 1 ,
wherein the spontaneously polarizable layer has a planar shape; and
wherein the gate isolation has a curved and/or angled shape.
5 . The memory cell of claim 1 ,
wherein the spontaneously polarizable layer is disposed outside the recess.
6 . The memory cell of claim 1 ,
wherein a lateral dimension of the recess is the same as a lateral dimension of the first electrode.
7 . The memory cell of claim 1 ,
wherein a lateral dimension of the recess is less than a lateral dimension of the second electrode; and
wherein a lateral dimension of the recess is less than a lateral dimension of the spontaneously polarizable layer.
8 . The memory cell of claim 1 ,
wherein the spontaneously polarizable layer is in direct physical contact with the first electrode and the second electrode.
9 . The memory cell of claim 1 ,
wherein the spontaneously polarizable layer comprises one or more sublayers of a remanent-polarizable material; or
wherein the spontaneously polarizable layer comprises at least one sublayer of a remanent-polarizable material and at least one additional dielectric layer.
10 . The memory cell of claim 1 ,
wherein the spontaneously polarizable layer, the first electrode, and the second electrode form a capacitive memory structure of the memory cell; and
wherein the semiconductor layer, the first source/drain region, the second source/drain region, the floating gate, and the gate isolation form a field-effect transistor structure of the memory cell; and
wherein the capacitive memory structure and the field-effect transistor structure are arranged in a capacitive voltage divider configuration.
11 . The memory cell of claim 10 ,
wherein a capacitance ratio of the capacitive voltage divider configuration is defined by a depth of the recess.
12 . The memory cell of claim 1 ,
wherein the semiconductor layer comprises a well region, and wherein the recess is formed in the well region.
13 . The memory cell of claim 1 ,
wherein the semiconductor layer comprises a well region and a deep well region, wherein the well region is disposed between the first and second source/drain regions and the deep well region, and wherein the recess is formed in the well region, wherein a portion of the well region separates the gate isolation disposed in the recess from the deep well region.
14 . The memory cell of claim 13 , further comprising:
an isolation structure disposed in the semiconductor layer, wherein the isolation structure extends through the well region to the deep well region.
15 . The memory cell of claim 1 ,
wherein the first electrode is in direct physical contact with the floating gate, and/or
wherein the first electrode is in direct physical contact with the gate isolation.
16 . The memory cell of claim 1 ,
wherein the spontaneously polarizable layer is in direct physical contact with the gate isolation.
17 . The memory cell of claim 1 ,
wherein the spontaneously polarizable layer has a lateral dimension that is greater than a lateral dimension of the first electrode; and/or
wherein the spontaneously polarizable layer has a lateral dimension that is greater than a lateral dimension of the floating gate.
18 . The memory cell of claim 1 ,
wherein the spontaneously polarizable layer has a first lateral dimension in a first region thereof and a second lateral dimension different from the first lateral dimension in a second region thereof.
19 . A memory cell comprising:
a field-effect transistor structure, the field-effect transistor structure comprising a gate structure to control a current flow in a channel, the gate structure comprising a gate isolation and a floating gate, wherein at least a part of the gate structure extends from a surface of a semiconductor layer into the semiconductor layer; and
a capacitive memory structure, the capacitive memory structure comprising at least two electrodes and a spontaneously polarizable layer disposed between the at least two electrodes, wherein at least a first electrode of the at least two electrodes is at least partially disposed in a recess of the semiconductor layer and wherein the spontaneously polarizable layer is disposed over the surface of the semiconductor layer.
20 . A memory cell arrangement comprising:
a plurality of memory cells arranged in an AND configuration or in a NOR configuration; each memory cell of the plurality of memory cells comprising:
a field-effect transistor structure, the field-effect transistor structure comprising a gate structure to control a current flow in a channel, the gate structure comprising a gate isolation and a floating gate, wherein at least a part of the gate structure extends from a surface of a semiconductor layer into the semiconductor layer; and
a capacitive memory structure, the capacitive memory structure comprising at least two electrodes and a spontaneously polarizable layer disposed between the at least two electrodes, wherein at least a first electrode of the at least two electrodes is at least partially disposed in a recess of the semiconductor layer and wherein the spontaneously polarizable layer is disposed over the surface of the semiconductor layer.