Ferroelectric memory circuit and reading method thereof
A ferroelectric memory circuit ( 100 ) includes: a memory cell ( 102 ), wherein a memory state ( 102 s ) of the memory cell ( 102 ) is switchable between a first memory state and a second memory state, the memory cell ( 102 ) further configured to output an electrical current ( 101 ) in response to receiving a readout voltage ( 103 ); and a sense circuit ( 104 ) configured to output an output voltage ( 105 ) based on the result of integrating the electrical current ( 101 ) output by the memory cell ( 102 ), wherein the output voltage ( 105 ) represents whether the memory state ( 102 s ) is the first memory state or the second memory state.
1. A memory cell circuit, comprising:
a memory cell, wherein a memory state of the memory cell is switchable between a first memory state and a second memory state, the memory cell further configured to output an electrical current in response to receiving a readout voltage; and
a sense circuit configured to output an output voltage based on the electrical current output by the memory cell, wherein the output voltage represents whether the memory state is the first memory state or the second memory state, wherein the sense circuit comprises a single-input inverter and an integrating capacitor, wherein the integrating capacitor couples an input node of the single-input inverter to an output of the single-input inverter that inverts signals as between the input node and the output,
wherein the single-input inverter comprises a first transistor pair cascaded with a second transistor pair, wherein the input node comprises connected gates of a first transistor of the first transistor pair and of a first transistor of the second transistor pair, wherein the output of the single-input inverter is connected between a second transistor of the first transistor pair cascaded with a second transistor of the second transistor pair, wherein a gate of the second transistor of the first transistor pair is connected to a first control terminal that is separate from the input node, wherein a gate of the second transistor of the second transistor pair is connected to a second control terminal that is separate from the input node,
wherein the first transistor of the first transistor pair is connected to a supply voltage and remains connected to the supply voltage even when the second transistor of the first transistor pair is switched off, wherein the first transistor of the second transistor pair is connected to a reference voltage and remains connected to the reference voltage when the second transistor of the second transistor pair is switched off.
2. The memory cell circuit of claim 1 , further comprising: a supply circuit configured to apply the readout voltage to the memory cell.
3. The memory cell circuit of claim 1 , wherein the sense circuit is configured to integrate the electrical current and to provide the output voltage based on a result of the integrating of the electrical current.
4. The memory cell circuit of claim 1 , wherein the integrating capacitor comprises a capacitance, wherein the sense circuit is configured to charge or discharge the capacitance by the electrical current, wherein the output voltage is based on a result of the charging or discharging the capacitance, wherein the result of the charging or discharging the capacitance comprises a voltage.
5. The memory cell circuit of claim 4 , wherein the single-input inverter is configured to convert the result of the charging or discharging of the capacitance into the output voltage.
6. The memory cell circuit of claim 1 , wherein the single-input inverter comprises a first transistor cascaded with a second transistor, between which the output of the single-input inverter is coupled, wherein the input node comprises gates of the first and second transistors connected together.
7. The memory cell circuit of claim 1 , wherein:
the first control terminal coupled that sets a first output voltage level of the single-input inverter, and
the second control terminal sets a second output voltage level of the single-input inverter.
8. The memory cell circuit of claim 4 , wherein the sense circuit comprises at least one switch coupled in parallel to the integrating capacitor to selectively reset the capacitance of the capacitor.
9. The memory cell circuit of claim 1 , wherein the readout voltage is configured to switch the memory state from the first memory state to the second memory state.
10. The memory cell circuit of claim 1 , wherein the readout voltage is configured such that memory state maintains the second memory state, when the readout voltage is received.
11. The memory cell circuit of claim 1 , further comprising:
an analog-to-digital converter configured to convert the output voltage into a digital representative of the memory state.
12. The memory cell circuit of claim 1 , wherein the memory cell comprises a ferroelectric capacitor, or wherein the memory cell is a ferroelectric capacitor.
13. The memory cell circuit of claim 1 , wherein the electrical current comprises a first characteristic when the memory state is switched; and wherein the electrical current comprises of second characteristic when the memory state is maintained.
14. The memory cell circuit of claim 1 , further comprising:
a dummy memory cell configured to output a further electrical current in response to receiving a further readout voltage and/or the readout voltage,
wherein the sense circuit is further configured to output the output voltage based on the further electrical current.
15. A memory cell circuit, comprising:
a set of memory cells, a first control line connecting the memory cells of the set of memory cells;
a set of second control lines, each second control being connected to a respective memory cell of the set of memory cells,
wherein a memory state of each of the memory cell is switchable between a first memory state and a second memory state, the memory cell further configured to output an electrical current via the first control line in response to receiving a readout voltage via one of the second control lines; and
a sense circuit configured to output an output voltage based on the electrical current output by the memory cell, wherein the output voltage represents whether the memory state is the first memory state or the second memory state, wherein the sense circuit comprises a single-input inverter and an integrating capacitor, wherein the integrating capacitor couples an input the of the single-input inverter to an output of the single-input inverter,
wherein the single-input inverter inverts signals as between the input node and the output, wherein the single-input inverter comprises a first transistor pair cascaded with a second transistor pair, wherein the input node comprises connected gates of a first transistor of the first transistor pair and of a first transistor of the second transistor pair, wherein the output of the single-input inverter is connected between a second transistor of the first transistor pair cascaded with a second transistor of the second transistor pair, wherein a gate of the second transistor of the first transistor pair is connected to a first control terminal that is separate from the input node, wherein a gate of the second transistor of the second transistor pair is connected to a second control terminal that is separate from the input node,
wherein the first transistor of the first transistor pair is connected to a supply voltage and remains connected to the supply voltage even when the second transistor of the first transistor pair is switched off, wherein the first transistor of the second transistor pair is connected to a reference voltage and remains connected to the reference voltage when the second transistor of the second transistor pair is switched off.