IP Library Granted Patent US 11,610,903
Granted Patent B2
US 11,610,903 · App. 17/213,797 · Granted Mar 21, 2023

Capacitive memory structure, functional layer, electronic device, and methods thereof

Inventor: Tony Schenk (Dresden, DE)
Assignee: FERROELECTRIC MEMORY GMBH
H01L27/11507H01L21/02356H01L28/60
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Quick Facts
Patent No.
US 11,610,903
App. No.
17/213,797
Granted
Mar 21, 2023
Kind
B2
Abstract

Various aspects relate to a functional layer and the formation thereof. A method for manufacturing a functional layer of an electronic device may include: forming a plurality of sublayers of the functional layer by a plurality of consecutive sublayer processes, each sublayer process of the plurality of consecutive sublayer processes comprising: forming a sublayer of the plurality of sublayers by vapor deposition, the sublayer comprising one or more materials, and, subsequently, crystallizing the one or more materials comprised in the sublayer.

Claims (51)

1. A method for manufacturing a memory layer of an electronic device, the method comprising:

forming a plurality of sublayers of the memory layer by a plurality of consecutive sublayer processes, wherein each sublayer is spontaneously polarizable and wherein a first sublayer of the plurality of sublayers is formed on an electrode, each sublayer process of the plurality of consecutive sublayer processes comprising:

forming a sublayer by vapor deposition, the sublayer comprising one or more materials, and, subsequently,

crystallizing the one or more materials comprised in the sublayer, wherein crystallizing the one or more materials comprised in the sublayer comprises generating a textured sublayer and wherein the textured sublayer has at least one of an (001) texture or a (111) texture.

2. The method according to claim 1 ,

wherein the one or more materials comprised in the sublayer are one or more metal oxides, or

wherein the one or more materials comprised in the sublayer are one or more metal nitrides.

3. The method according to claim 1 ,

wherein the one or more materials comprised in the sublayer are one or more transition metal oxides, or

wherein the one or more materials comprised in the sublayer are one or more transition metal nitrides.

4. The method according to claim 3 ,

wherein forming the sublayer by vapor deposition comprises depositing the one or more transition metal oxides and, subsequently, doping the one or more transition metal oxides; or

wherein the one or more one or more materials comprised in the sublayer are one or more doped transition metal oxides.

5. The method according to claim 1 ,

wherein, prior to crystallizing the one or more materials comprised in the sublayer, the one or more materials comprised in the sublayer are one or more amorphous materials; and

wherein, subsequent to crystallizing the one or more materials comprised in the sublayer, the one or more materials comprised in the sublayer are one or more single crystalline or polycrystalline materials.

6. The method according to claim 1 ,

wherein crystallizing the one or more materials comprised in the sublayer comprises increasing a crystallinity of one or more materials of the sublayer.

7. The method according to claim 6 ,

wherein increasing the crystallinity of the one or more materials of the sublayer comprises an increase of an average grain size of the one or more materials of the sublayer; and/or

wherein increasing the crystallinity of the one or more materials of the sublayer comprises a reduction of a total number of grains of the one or more materials comprised in the sublayer.

8. The method according to claim 1 ,

wherein crystallizing the one or more materials comprised in the sublayer comprises thermally annealing the sublayer.

9. The method according to claim 1 ,

wherein the sublayer has a layer thickness in the range from about 0.5 nm to about 5 nm.

10. The method according to claim 1 ,

wherein a layer thickness of the memory layer is defined by a total number of sublayers of the memory layer and respective layer thicknesses of the sublayers.

11. The method according to claim 1 ,

wherein the vapor deposition comprises at least one of atomic layer deposition or sputter deposition.

12. The method according to claim 1 ,

wherein the one or more materials comprised in each sublayer are one or more spontaneously polarizable materials.

13. Method for manufacturing a capacitive memory structure, the method comprising:

forming a first electrode of the capacitive memory structure,

forming a second electrode of the capacitive memory structure, and

forming a spontaneously polarizable memory layer of the capacitive memory structure, wherein the spontaneously polarizable memory layer is at least partially disposed between the first electrode and the second electrode and wherein the spontaneously polarizable memory layer is in direct physical contact with both the first electrode and the second electrode, and wherein forming the spontaneously polarizable memory layer comprises:

depositing one or more materials by vapor deposition, and

crystallizing the deposited one or more materials to form a first sublayer of the spontaneously polarizable memory layer, and, subsequently,

depositing one or more materials by vapor deposition, and

crystallizing the deposited one or more materials to form a second sublayer of the spontaneously polarizable memory layer.

14. The method according to claim 13 ,

wherein the one or more materials comprise one or more transition-metal-oxides; or

wherein the one or more materials comprise one or more transition-metal-nitrides.

15. The method according to claim 13 ,

wherein the one or more materials of the first sublayer are distinct from the one or more materials of the second sublayer; and wherein crystallizing the deposited one or more materials of the first sublayer is carried out by a first annealing temperature and crystallizing the deposited one or more materials of the second sublayer is carried out by a second annealing temperature distinct from the first annealing temperature.

16. The method according to claim 13 ,

wherein the one or more materials of the first sublayer are the same as the one or more materials of the second sublayer; and wherein crystallizing the deposited one or more materials of the first sublayer is carried out by a first annealing temperature and wherein crystallizing the deposited one or more materials of the second sublayer is carried out by the first annealing temperature.

17. The method according to claim 1 , wherein each sublayer process of the plurality of consecutive sublayer processes further comprises:

forming a further sublayer by vapor deposition, the further sublayer comprising one or more further materials distinct from the one or more materials of the sublayer, and, subsequently,

crystallizing the one or more further materials comprised in the further sublayer.

18. The method according to claim 1 , wherein forming the sublayer comprises:

depositing a first transition-metal-oxide layer, depositing a second transition-metal-oxide layer, and forming an insulating layer at least partially disposed between the first transition-metal-oxide layer and the second transition-metal-oxide layer; and wherein crystallizing the one or more materials comprised in the sublayer comprises crystallizing both the first transition-metal-oxide layer and the second transition-metal-oxide layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2021
From: SCHENK, TONY
To: FERROELECTRIC MEMORY GMBH
Reel/Frame 056200/0462 →
Continuity (1)
Related Publication 20220173114A1 · Jun 2, 2022
Cited By (5)
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