Multi-stack ferroelectric memory structure
Various aspects relate to a memory device including: a plurality of gate layer stacks, wherein each gate layer stack of the plurality of gate layer stacks includes a gate electrode layer and one or more electrically insulating layers; one or more channel structures extending through the plurality of gate layer stacks, wherein the plurality of gate layer stacks and the one or more channel structures correspond to a plurality of field-effect transistor based memory cells, wherein each field-effect transistor based memory cell of the plurality of field-effect transistor based memory cells includes: a gate layer portion of a gate layer stack of the plurality of gate layer stacks; a channel portion of a channel structure of the one or more channel structures; a spontaneously-polarizable portion; and a floating gate, wherein the spontaneously-polarizable portion and the floating gate are disposed between the gate layer portion and the channel portion.
1. A memory device comprising:
a plurality of gate layer stacks, wherein each gate layer stack of the plurality of gate layer stacks comprises a gate electrode layer and one or more electrically insulating layers;
one or more channel structures extending through the plurality of gate layer stacks,
wherein the plurality of gate layer stacks and the one or more channel structures correspond to a plurality of field-effect transistor based memory cells of the memory device,
wherein a first field-effect transistor based memory cell of the plurality of field-effect transistor based memory cells comprises:
a first gate layer portion of a first gate layer stack of the plurality of gate layer stacks;
a first channel portion of a channel structure of the one or more channel structures;
a spontaneously-polarizable portion; and
a first floating gate,
wherein the spontaneously-polarizable portion and the first floating gate are disposed between the first gate layer portion and the first channel portion, and
wherein a height of the spontaneously-polarizable portion is less than a height of the first floating gate when measured along an axis parallel to a longitudinal axis of the one or more channel structures.
2. The memory device according to claim 1 ,
wherein a second field-effect transistor based memory cell of the plurality of field-effect transistor based memory cells comprises a second floating gate and a second channel portion of the channel structure, and
wherein the first field-effect transistor based memory cell and the second field-effect transistor based memory cell correspond to the first gate layer stack of the plurality of gate layer stacks.
3. The memory device according to claim 2 ,
wherein the first floating gate is disposed at a first side of the channel structure,
wherein the second floating gate is disposed at a second side of the channel structure, and
wherein the first side is opposite to the second side.
4. The memory device according to claim 1 ,
wherein the memory device further comprises one or more gate separation layers, and
wherein adjacent gate layer stacks of the plurality of gate layer stacks are separated from one another by a gate separation layer of the one or more gate separation layers.
5. The memory device according to claim 4 ,
wherein the one or more electrically insulating layers comprise a first electrically insulating material and the one or more gate separation layers comprise a second electrically insulating material different from the first electrically insulating material.
6. The memory device according to claim 1 ,
wherein at least one channel structure of the one or more channel structures comprises at least two semiconductor portions, and
wherein the at least one channel structure comprises at least one separation portion disposed between the at least two semiconductor portions.
7. The memory device according to claim 1 ,
wherein a second gate layer stack of the plurality of gate layer stacks comprises a second gate layer portion corresponding to a second field-effect transistor based memory cell of the plurality of field-effect transistor based memory cells, and
wherein the first gate layer portion and the second gate layer portion are spaced from one another along a vertical direction.
8. The memory device according to claim 7 ,
wherein a third gate layer stack further comprises a third gate layer portion corresponding to a third field-effect transistor based memory cell of the plurality of field-effect transistor based memory cells, and
wherein the first gate layer portion and the third gate layer portion are spaced from one another along a lateral direction.
9. The memory device according to claim 1 ,
wherein the one or more channel structures extend through the plurality of gate layer stacks along a vertical direction.
10. The memory device according to claim 1 ,
wherein the spontaneously-polarizable portion is U-shaped around the first floating gate of the first field-effect transistor based memory cell.
11. The memory device according to claim 1 ,
wherein the spontaneously-polarizable portion completely laterally surrounds at least three sidewalls of the first floating gate of the first field-effect transistor based memory cell.
12. The memory device according to claim 1 ,
wherein each field-effect transistor based memory cell of the plurality of field-effect transistor based memory cells has a first capacitance and a second capacitance associated therewith,
wherein the first capacitance is associated with a first spontaneously-polarizable portion of the field-effect transistor based memory cell, and
wherein the second capacitance is associated with a channel portion associated with the field-effect transistor based memory cell.
13. The memory device according to claim 1 ,
wherein the memory device further comprises one or more channel-isolation structures, and
wherein the one or more channel-isolation structures laterally surround a sidewall of the one or more channel structures.
14. The memory device according to claim 13 ,
wherein a first channel-isolation structure of the one or more channel-isolation structures is disposed between a first channel structure of the one or more channel structures and a floating gate corresponding to the first channel structure.
15. A memory device comprising:
a first memory cell and a second memory cell,
wherein the first memory cell comprises a first gate layer portion,
wherein the first gate layer portion comprises a first gate electrode layer and one or more first electrically insulating layers,
wherein the second memory cell comprises a second gate layer portion,
wherein the second gate layer portion comprises a second gate electrode layer and one or more second electrically insulating layers; and
a channel structure extending through the first gate layer portion and the second gate layer portion,
wherein the channel structure comprises a first channel portion associated with the first memory cell and further comprises a second channel portion associated with the second memory cell,
wherein the first memory cell further comprises a first spontaneously-polarizable portion and a first floating gate, wherein the first spontaneously-polarizable portion and the first floating gate are disposed between the first gate layer portion and the first channel portion,
wherein the second memory cell further comprises a second spontaneously-polarizable portion and a second floating gate, wherein the second spontaneously-polarizable portion and the second floating gate are disposed between the second gate layer portion and the second channel portion,
wherein the first gate layer portion, the first floating gate, and the first channel portion form a first field-effect transistor structure,
wherein the second gate layer portion, the second floating gate, and the second channel portion form a second field-effect transistor structure,
wherein a height of the first spontaneously-polarizable portion is less than a height of the first floating gate when measured along an axis parallel to a longitudinal axis of the channel structure, and
wherein a height of the second spontaneously-polarizable portion is less than a height of the second floating gate when measured along the axis parallel to the longitudinal axis of the channel structure.
16. The memory device according to claim 15 ,
wherein the first memory cell and the second memory cell are spaced apart from one another along a vertical direction.
17. A memory device comprising:
a plurality of gate layer stacks, wherein each gate layer stack of the plurality of gate layer stacks comprises a gate electrode layer and one or more electrically insulating layers; and
one or more channel structures extending through the plurality of gate layer stacks,
wherein the plurality of gate layer stacks and the one or more channel structures correspond to a plurality of field-effect transistor based memory cells of the memory device,
wherein a first field-effect transistor based memory cell of the plurality of field-effect transistor based memory cells comprises:
a first gate layer portion of a first gate layer stack of the plurality of gate layer stacks;
a first channel portion of a channel structure of the one or more channel structures;
a spontaneously-polarizable portion; and
a first floating gate,
wherein the spontaneously-polarizable portion and the first floating gate are disposed between the first gate layer portion and the first channel portion, and
wherein the spontaneously-polarizable portion is U-shaped around the first floating gate of the first field-effect transistor based memory cell.
18. The memory device of claim 17 , wherein the spontaneously-polarizable portion being U-shaped around the first floating gate of the first field-effect transistor based memory cell comprises the spontaneously-polarizable portion contacting at least two sides of the floating gate.
19. The memory device according to claim 17 ,
wherein a second field-effect transistor based memory cell of the plurality of field-effect transistor based memory cells comprises a second floating gate and a second channel portion of the channel structure, and
wherein the first field-effect transistor based memory cell and the second field-effect transistor based memory cell correspond to the first gate layer stack of the plurality of gate layer stacks.
20. The memory device according to claim 17 ,
wherein the first floating gate is disposed at a first side of the channel structure,
wherein the second floating gate is disposed at a second side of the channel structure, and
wherein the first side is opposite to the second side.