Method for forming gate-all-around structure

1. A method for forming a gate-all-around structure, comprising:

forming a plurality of a first type of semiconductor layers and a plurality of a second type of semiconductor layers alternately stacked over a fin, wherein the first type of semiconductor layers comprises a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer has a thickness greater than that of the second semiconductor layer;

removing the second type of semiconductor layers; and

forming a gate to wrap around the first type of semiconductor layers.

2. The method of claim 1 , wherein etching the first type of semiconductor layers during removing the second type of semiconductor layers.

3. The method of claim 2 , wherein the first semiconductor layer has a thickness substantially equal to that of the second semiconductor after etching.

4. The method of claim 1 , wherein removing the second type of semiconductor layers forms a first gap between the fin and the first semiconductor layer and a second gap between the first semiconductor layer and the second semiconductor layer, and the first gap is greater than the second gap.

5. The method of claim 4 , wherein removing the second type of semiconductor layers forms a third gap between the second semiconductor layer and a third semiconductor layer over the second semiconductor layer, and the second gap is greater than the third gap.

6. The method of claim 1 , wherein the first type of semiconductor layers comprises a third semiconductor layer over the second semiconductor layer, and the second semiconductor layer has a greater thickness than that of the third semiconductor layer.

7. The method of claim 6 , wherein the second semiconductor layer has a thickness substantially equal to that of the third semiconductor after removing the second type of semiconductor layers.

8. The method of claim 1 , wherein the first type of semiconductor layers include silicon germanium, and the second type of semiconductor layers include silicon.

9. A method for forming a gate-all-around structure, comprising:

forming a semiconductor stack over a semiconductor substrate, wherein the semiconductor stack has a plurality of a first type of semiconductor layers and a plurality of a second type of semiconductor layers stacked alternately;

patterning the semiconductor stack to form a fin;

forming a dummy gate stack across a portion of the fin;

removing the dummy gate stack and the second type of semiconductor layers to form a first nanowire, a second nanowire over the first nanowire and a third nanowire over the second nanowire, wherein a first space between the first nanowire and the second nanowire is greater than a second space between the second nanowire and the third nanowire; and

forming a gate wrapping around the first nanowire, the second nanowire and the third nanowire.

10. The method of claim 9 , wherein forming the dummy gate stack comprises:

forming an oxide layer over the fin; and forming a dummy gate over the oxide layer.

11. The method of claim 9 , wherein removing the dummy gate stack and the second type of semiconductor layers forms a fourth nanowire over the third nanowire, and a second space between the second nanowire and the third nanowire is greater than a third space between the third nanowire and the fourth nanowire.

12. The method of claim 9 , further comprising: forming a source/drain to wrap around the first nanowire, the second nanowire and the third nanowire.

13. The method of claim 9 , further comprising: forming a sacrificial layer on the semiconductor substrate before forming the semiconductor stack; implanting the semiconductor substrate to form a first well region abutting the sacrificial layer; and removing the sacrificial layer during removing the dummy gate stack and the second type of semiconductor layers.

14. The method of claim 13 , further comprising: implanting the semiconductor substrate to form a second well region between the sacrificial layer and the first well region, wherein the second well region and the first well region have different type of dopants.

15. The method of claim 14 , wherein a thickness of the second well region is less than a thickness of the first well region.

16. A method for forming a gate-all-around structure, comprising:

forming first nanowire material stack and second nanowire material stack over a top surface of a substrate;

patterning the first nanowire material stack and second nanowire material stack and the substrate to form semiconductor fins separated from each other by an isolation;

forming a dummy gate orthogonally over the semiconductor fins;

selectively removing the first nanowire material not covered by the dummy gate thereby exposing a second nanowire at a source/drain region;

removing the dummy gate; and selectively removing the first nanowire material previously covered by the dummy gate thereby exposing the second nanowire at a channel region, wherein the size of a first space between a first layer of the second nanowire over the top surface and a second layer of the second nanowire over the first layer of the second nanowire is different from a second space between the second layer of the second nanowire and a third layer of the second nanowire over the second layer of the second nanowire.

17. The method of claim 16 , wherein forming the first nanowire material and second nanowire material stack comprises:

forming a first layer of the first nanowire material over the top surface, the first layer of the first nanowire material having a first thickness;

forming the first layer of the second nanowire material over the first layer of the first nanowire material, the first layer of the second nanowire material having a second thickness; forming an N th layer of the first nanowire material over the first layer of the second nanowire material, N being an integer greater than 1, the N th layer of the first nanowire material having a third thickness; forming an N th layer of the second nanowire material over N th layer of the first nanowire material, the N th layer of the second nanowire material having a fourth thickness, forming an (N+1) th layer of the first nanowire material over the N th layer of the second nanowire material, the (N+1) th layer of the first nanowire material having a fifth thickness; and

forming an (N+1) th layer of the second nanowire material over the (N+1) th layer of the first nanowire material, the (N+1) th layer of the second nanowire material having a sixth thickness, wherein the first thickness is greater than the third thickness, and the second thickness is greater than the fourth thickness.

18. The method of claim 16 , wherein the first space is greater than the second space.

19. The method of claim 16 , wherein the first space is at least greater than the second space by 1 nm.

20. The method of claim 16 , further comprising forming a gate filling the first space and the second space at the channel region.