Multi-bit memory system with adaptive read voltage controller
According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.
1. A memory system comprising:
a semiconductor memory including a first word line and a first memory cell coupled to the first word line, the first memory cell being capable of holding multi-bit data including a first bit and a second bit; and
a controller configured to issue a first command and a second command, wherein
in response to the issued first command, the semiconductor memory is configured to execute a first reading operation, the first reading operation including applying a voltage within a first range and a voltage within a second range to the first word line and reading a first data item from the first memory cell, the first data item corresponding to the first bit,
in response to the issued second command, the semiconductor memory is configured to execute a second reading operation, the second reading operation applying a voltage between the first range and the second range to the first word line and reading a second data item from the first memory cell,
the controller is configured to determine a first voltage within the first range based on at least the first data item and the second data item,
the controller is configured to determine a second voltage within a third range based on at least the first voltage, the third range being different from the first range and the second range, the second voltage being for reading the second bit,
the controller is configured to issue a third command, and
in response to the issued third command, the semiconductor memory is configured to apply the second voltage to the first word line and read a third data item from the first memory cell, the third data item corresponding to the second bit.
2. The memory system of claim 1 , wherein
the controller is configured to issue the first command a plurality of times and change the voltage within the first range and the voltage within the second range in accordance with the plurality of first commands, and
the controller is configured to determine the first voltage based on a first bit count based on at least a plurality of first data items and the second data item, each of the plurality of the first data items corresponding to each of the plurality of first commands.
3. The memory system of claim 2 , wherein
the semiconductor memory is configured to generate each of a plurality of third bits based on at least each of the plurality of the first data items and the second data item, each of the plurality of third bits corresponding to each of the first data items, and
the controller is configured to generate the first bit count based on the plurality of third bits.
4. The memory system of claim 2 , wherein
the semiconductor memory is configured to generate each of a plurality of fifth bits based on at least each of the plurality of the first data items and the second data item, each of the plurality of fifth bits corresponding to each of the plurality of the first data items, and
the controller is configured to generate a second bit count based on the plurality of fifth bits and determine a third voltage within the second range based on the second bit count.
5. The memory system of claim 4 , wherein the controller is configured to determine the second voltage within a third range based on a difference between the first voltage and the third voltage.
6. The memory system of claim 4 , wherein the controller is configured to determine the second voltage within a third range based on an intermediate voltage between the first voltage and the third voltage.
7. The memory system of claim 2 , wherein
the number of the plurality of times is at least four times,
the voltage within the first range in a second time of the plurality of times is lower than the voltage within the first range in a first time of the plurality of times,
the voltage within the first range in a third time of the plurality of times is lower than the voltage within the first range in the second time of the plurality of times,
the voltage within the second range in the second time of the plurality of times is lower than the voltage within the second range in the first time of the plurality of times, and
the voltage within the second range in the third time of the plurality of times is lower than the voltage within the second range in the second time of the plurality of times.
8. The memory system of claim 2 , wherein
the first reading operation includes further applying a voltage within a fourth range to the first word line,
the controller is configured to issue further a fourth command,
in response to the issued fourth command, the semiconductor memory is configured to execute a third reading operation, the third reading operation applying a voltage within between the second range and the fourth range to the first word line and read a fourth data item from the first memory cell,
the first bit count is generated based on the plurality of first data items, the second data item and the fourth data item, and
the controller is configured to determine the first voltage based on the generated first bit count.
9. The memory system of claim 8 , wherein
the semiconductor memory is configured to generate each of a plurality of fourth bits based on each of the first data items, the second data item, and the fourth data item, each of the plurality of fourth bits corresponding to each of the first data items, and
the controller is configured to generate the first bit count based on the plurality of fourth bits.
10. The memory system of claim 9 , wherein
the semiconductor memory further includes a first latch, a second latch, and a third latch,
the semiconductor memory is configured to store the second data item in the first latch, store the fourth data item in the second latch, and store one of the first data items in the third latch,
the semiconductor memory is configured to generate one of the plurality of fourth bits based on the second data item in the first latch, the fourth data item in the second latch, and the one of the first data items in the third latch, and
the semiconductor memory is configured to send each of the plurality of the fourth bits to the controller.
11. The memory system of claim 1 , wherein the controller is configured to determine the second voltage based on a difference between the first voltage and a fourth voltage within the first range.
12. The memory system of claim 1 , wherein
the semiconductor memory further includes a second word line and a second memory cell coupled to the second word line,
the first memory cell and the second memory cell are connected in series, and
in response to the issued third command, the semiconductor memory is configured to apply, to the second word line, a fourth voltage and a fifth voltage during which the second voltage is applied to the first word line, the fifth voltage being different from the fourth voltage.
13. The memory system of claim 12 , wherein
the semiconductor memory is configured to sequentially apply to the second word line, the fourth voltage and the fifth voltage, and
the fifth voltage is higher than the fourth voltage.
14. The memory system of claim 13 , wherein the second memory cell is capable of holding multi-bit data including the first bit and the second bit.