Memory device and non-transitory computer readable recording medium

1. A memory device, comprising:

a nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and configured to:

generate first information including a logical address associated with valid data written in a first area of the nonvolatile memory,

transmit the first information to a host device, and

in response to receiving, from the host device, second information that is received after the first information is transmitted to the host device, the second information specifying a logical address associated with data to be deleted amongst the valid data in the first area,

perform garbage collection on the first area such that first data is copied to a second area of the nonvolatile memory but second data is not copied to the second area of the nonvolatile memory, the first data being the valid data written in the first area and not specified in the second information as the data to be deleted, the second data being the valid data written in the first area and specified in the second information as the data to be deleted, the second area being different from the first area.

2. The memory device of claim 1 , wherein

the controller is further configured to generate third information indicating whether data written in the nonvolatile memory is valid or invalid, and generate the first information based on the third information.

3. The memory device of claim 2 , wherein

the controller is further configured to generate fourth information relating a logical address of write data written in the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory, and generate the third information based on the fourth information.

4. The memory device of claim 2 , wherein

the controller is configured to perform, based on the second information and the third information, the garbage collection on the first area.

5. The memory device of claim 1 , wherein

the valid data is updated data in a case where update of the data written in the nonvolatile memory is performed.

6. The memory device of claim 1 , wherein

the host device includes a processor, and

the data to be deleted is data for which a delete command has been issued by the processor executing an application program or an operating system.

7. The memory device of claim 1 , wherein

the first area of the nonvolatile memory is a candidate for the garbage collection.

8. The memory device of claim 1 , wherein

the first information further includes an identifier of the first area of the nonvolatile memory.

9. The memory device of claim 8 , wherein

the second information includes the identifier of the first area of the nonvolatile memory.

10. The memory device of claim 1 , wherein

the nonvolatile memory includes a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation, and

the first area is one of the plurality of blocks.

11. A control method of a memory device, the memory device including a nonvolatile memory, the control method comprising:

generating first information including a logical address associated with valid data written in a first area of the nonvolatile memory;

transmitting the first information to a host device communicating with the memory device; and

in response to receiving, from the host device, second information that is received after the first information is transmitted to the host device, the second information specifying a logical address associated with data to be deleted amongst the valid data in the first area,

performing garbage collection on the first area such that first data is copied to a second area of the nonvolatile memory but second data is not copied to the second area of the nonvolatile memory, the first data being the valid data written in the first area and not specified in the second information as the data to be deleted, the second data being the valid data written in the first area and specified in the second information as the data to be deleted, the second area being different from the first area.

12. The control method of claim 11 , further comprising:

generating third information indicating whether data written in the nonvolatile memory is valid or invalid, wherein

the first information is generated based on the third information.

13. The control method of claim 12 , further comprising:

generating fourth information relating a logical address of write data written in the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory, wherein

the third information is generated based on the fourth information.

14. The control method of claim 12 , wherein

the garbage collection on the first area is performed based on the second information and the third information.

15. The control method of claim 11 , wherein

the valid data is updated data in a case where update of the data written in the nonvolatile memory is performed.

16. The control method of claim 11 , wherein

the host device includes a processor, and

the data to be deleted is data for which a delete command has been issued by the processor executing an application program or an operating system.

17. The control method of claim 11 , further comprising:

receiving the first information by the host device;

after receiving the first information, generating the second information based on the first information by the host device; and

transmitting the second information to the memory device by the host device.

18. The control method of claim 11 , wherein

the first information further includes an identifier of the first area of the nonvolatile memory.

19. The control method of claim 18 , wherein

the second information includes the identifier of the first area of the nonvolatile memory.

20. The control method of claim 11 , wherein

the nonvolatile memory includes a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation, and

the first area is one of the plurality of blocks.