Data compression and encryption based on translation lookaside buffer evictions
A processing system selectively compresses cache lines at a cache or at a memory or encrypts cache lines at the memory based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and selectively compresses the cache lines to increase the effective storage capacity of the processing system or encrypts the cache lines to protect against vulnerabilities.
1. A method comprising:
communicating, at a translation lookaside buffer (TLB) of a processor, a memory page address corresponding to a TLB entry to a cache logic of a cache or a memory controller of a memory in response to the TLB entry being evicted from the TLB; and
at the cache logic or at the memory controller, selecting, for at least one of compression and encryption, one or more cache lines of the cache or of the memory corresponding to the memory page address in response to receiving the communication.
2. The method of claim 1 , wherein selecting comprises:
walking the cache to identify one or more cache lines corresponding to the memory page address; and
compressing the one or more cache lines at the cache.
3. The method of claim 2 , wherein walking comprises:
identifying a subset of the cache that contains cache lines that potentially map to the memory page address corresponding to the TLB entry; and
walking the subset of the cache to identify one or more cache lines corresponding to the memory page address.
4. The method of claim 2 , wherein walking comprises walking the cache to identify one or more cache lines corresponding to the memory page address only during cycles in which the cache logic is not processing other requests.
5. The method of claim 1 , wherein selecting comprises encrypting the one or more cache lines at the memory.
6. The method of claim 1 , further comprising:
measuring a performance characteristic of the processor; and wherein
selecting comprises selectively encrypting at the memory or compressing at the cache or at the memory the one or more cache lines according to a memory management policy implemented at the cache or at the memory based on the measured performance characteristic.
7. The method of claim 1 , further comprising:
storing the memory page address at a register;
in response to accessing a cache line at a set, comparing tags of cache lines of the set to the memory page address stored at the register; and
wherein selecting comprises compressing or encrypting cache lines of the set that match the memory page address stored at the register.
8. The method of claim 1 , wherein:
communicating comprises broadcasting a notification of the TLB entry eviction to a plurality of memory controllers, each memory controller associated with a memory of the processor; and
selecting comprises, at each memory controller of the plurality of memory controllers, encrypting cache lines of each associated memory corresponding to the memory page address.
9. A method, comprising:
in response to eviction of a translation lookaside buffer (TLB) entry indicating a virtual-to-physical address translation from a TLB of a processor, selectively compressing or encrypting cache lines storing data having addresses corresponding to a physical address at a memory or a virtual address of the TLB entry.
10. The method of claim 9 , further comprising:
walking a cache to identify cache lines corresponding to the physical address or virtual address of the TLB entry; and wherein selectively compressing or encrypting comprises compressing the cache lines at the cache.
11. The method of claim 10 , wherein walking comprises:
identifying a subset of cache lines that potentially map to the physical address or virtual address corresponding to the TLB entry; and
walking the subset of cache lines to identify cache lines corresponding to the physical address or virtual address.
12. The method of claim 10 , wherein walking comprises walking the cache to identify cache lines corresponding to the physical address or virtual address only during cycles in which cache logic of the cache is not processing other requests.
13. The method of claim 9 , wherein selectively compressing or encrypting comprises:
storing the physical address of the TLB entry at a queue; and
encrypting a cache line stored at the physical address only during cycles when the memory is idle.
14. The method of claim 9 , further comprising:
measuring a performance characteristic of the processor; and wherein
selectively compressing or encrypting comprises selectively encrypting the cache lines at a memory or compressing the cache lines at the memory or at a cache according to a memory management policy implemented at the cache or at the memory based on the performance characteristic.
15. The method of claim 9 , further comprising:
storing the physical address or virtual address at a register;
in response to accessing a cache line of a set of cache lines, comparing tags of cache lines of the set to the physical address or virtual address stored at the register; and
wherein selectively compressing or encrypting comprises compressing the cache lines of the set that match the physical address or virtual address stored at the register.
16. A processor, comprising:
a translation lookaside buffer (TLB);
a cache; and
cache logic configured to compress one or more cache lines of the cache storing data or instructions having an address corresponding to a physical or virtual address of an entry of the TLB in response to receiving a communication from the TLB that the entry of the TLB has been evicted.
17. The processor of claim 16 , further comprising:
a memory controller of a memory configured to encrypt one or more cache lines of the memory storing data or instructions having an address corresponding to the physical address of the entry of the TLB in response to receiving a communication from the TLB that the entry of the TLB has been evicted.
18. The processor of claim 17 , further comprising:
a performance monitor configured to measure a performance characteristic of the processor; and
wherein the cache logic is further configured to compress the one or more cache lines or the memory controller is further configured to encrypt the one or more cache lines according to a memory management policy implemented at the cache or at the memory based on the performance characteristic.
19. The processor of claim 16 , wherein the cache logic is configured to identify cache lines corresponding to the physical or virtual address by walking the cache only during cycles in which the cache logic is not processing other requests.
20. The processor of claim 16 , further comprising:
a register configured to store the physical or virtual address; and wherein
the cache logic is further configured to compare addresses of data or instructions stored at cache lines of a set to the physical or virtual address stored at the register in response to accessing a cache line of the set and compress cache lines of the set that match the physical or virtual address stored at the register.