IP Library Granted Patent US 11,393,967
Granted Patent B2
US 11,393,967 · App. 17/138,893 · Granted Jul 19, 2022

Eutectic electrode structure of flip-chip LED chip and flip-chip LED chip

Inventors: Anhe He (Xiamen, CN); Suhui Lin (Xiamen, CN); Jiansen Zheng (Xiamen, CN); Kangwei Peng (Xiamen, CN); Xiaoxiong Lin (Xiamen, CN); Chenke Hsu (Xiamen, CN)
Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
H01L33/62H01L24/13H01L24/14H01L33/40H01L24/06H01L24/16H01L24/81H01L2224/0401H01L2224/06102H01L2224/13006H01L2224/13011H01L2224/13016H01L2224/13017H01L2224/13018H01L2224/13019H01L2224/13082H01L2224/14051H01L2224/16227H01L2224/48506H01L2224/80805H01L2224/81191H01L2224/81805H01L2225/06513H01L2924/12041H01L2924/37001H01L2933/0016
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Quick Facts
Patent No.
US 11,393,967
App. No.
17/138,893
Granted
Jul 19, 2022
Kind
B2
Abstract

A light emitting diode includes: a light emitting structure including a first semiconductor layer, a light emitting layer arranged on at least part of the first semiconductor layer, a second semiconductor layer arranged on the light emitting layer; a first metal layer arranged on at least part of the first semiconductor layer and in contact with the first semiconductor layer; an insulating layer covered a surface of the light emitting structure; and an electrode layer arranged on the insulating layer and having at least one region that is not overlapped with the first metal layer or the second metal layer in a vertical direction.

Claims (54)

1. A light emitting diode, comprising:

a light emitting structure including a light emitting layer arranged on at least part of a first semiconductor layer, and a second semiconductor layer arranged on the light emitting layer;

a first metal layer arranged on at least part of the first semiconductor layer and in contact with the first semiconductor layer;

an insulating layer covering a surface of the light emitting structure; and

an electrode layer arranged on the insulating layer and having at least one region that is not overlapped with the first metal layer or the second metal layer in a vertical direction.

2. The light emitting diode of claim 1 , wherein the light emitting structure has a portion of defect region arranged in the second semiconductor layer, and extending downward to the first semiconductor layer to expose part of the first semiconductor layer, the first metal layer arranged on the portion of defect region, and the portion of defect region is not overlapped with the a first bonding region or the a second bonding region in a vertical direction.

3. The light emitting diode of claim 1 , wherein

the second semiconductor layer is a P type semiconductor layer; and

the first semiconductor layer is an N type semiconductor layer.

4. The light emitting diode of claim 1 , wherein the metal layer comprises at least one of Cr, Ti, Pt, Au, Ag, Ni, Cu, and TiW.

5. The light emitting diode of claim 1 , wherein the electrode layer comprises at least one of Ti, Ni, Cu, Au, AuSn, SnCu, and SnBi.

6. The light emitting diode of claim 1 , wherein the insulating layer comprises at least one of SiO 2 , Al 2 O 3 , SiN x , and TiO 2 .

7. The light emitting diode of claim 1 , wherein

the electrode layer comprises a second region electrode layer;

the second region electrode layer is arranged on at least part of the insulating layer and in contact with the second metal layer via one opening structure in the insulating layer; and

the second region electrode layer has at least one region not overlapped with the second metal layer.

8. The light emitting diode of claim 7 , wherein

the second region electrode layer comprises:

a metal contact region that is in contact with the second metal layer in the vertical direction; and

a non-metal contact region that is not contact with the second metal layer in the vertical direction, wherein the non-metal contact region is not overlapped with the second metal layer in the vertical direction.

9. The light emitting diode of claim 8 , wherein the non-metal contact region of the second region electrode layer is not overlapped with the metal contact region of the second region electrode layer in the vertical direction.

10. The light emitting diode of claim 1 , wherein

the electrode layer comprises a first region electrode layer which arranged on the insulating layer and in contact with the first metal layer via one opening structure in the insulating layer; and

the first region electrode layer has at least one region that is not overlapped with the first metal layer.

11. The light emitting diode of claim 10 , wherein

the first region electrode layer comprises:

a metal contact region that is in contact with the first metal layer in the vertical direction; and

a non-metal contact region that is not in contact with the first metal layer in the vertical direction, wherein the non-metal contact region is not overlapped with the first metal layer in the vertical direction.

12. The light emitting diode of claim 11 , wherein

the non-metal contact region of the first region electrode layer extends in the vertical direction to form a bonding region;

the bonding region is contact with at least part of a package substrate; and

the bonding region is not overlapped with the first metal layer in vertical direction.

13. The light emitting diode of claim 11 , wherein the non-metal contact region of the first region electrode layer is not overlapped with the metal contact region of the first region electrode layer in the vertical direction.

14. A light emitting diode, comprising:

a light emitting structure including a light emitting layer arranged on at least part of a first semiconductor layer, and a second semiconductor layer arranged on the light emitting layer;

a first metal layer arranged on at least part of the first semiconductor layer and in contact with the first semiconductor layer;

a second metal layer arranged over at least of the second semiconductor layer and in electrical contact the second semiconductor layer; and

an electrode layer arranged over the second semiconductor layer;

wherein the electrode layer has a bonding regions available for bonding with a package substrate;

wherein the bonding region includes a first bonding region electrically connected to the first semiconductor layer and a second bonding region electrically connected to the second semiconductor layer; and

wherein the first metal layer is not overlapped with first bonding region or the second bonding region in a vertical direction.

15. The light emitting diode of claim 14 , further comprising a transparent conducting layer arranged between the second semiconductor layer and the second metal layer.

16. The light emitting diode of claim 1 , wherein the second metal layer is not overlapped with first bonding region or the second bonding region in vertical direction.

17. The light emitting diode of claim 14 , further comprising an insulating layer arranged between the second metal layer and the electrode layer.

18. The light emitting diode of claim 14 , wherein the first metal layer has a portion arranged on the first semiconductor layer corresponding to a first region of a surface of the light emitting structure, and an extension portion extending from the first region of the surface to a second region of the surface.

19. The light emitting diode of claim 18 , wherein the first metal layer has a portion corresponding to the first region of the surface, and another portion corresponding to the second region of the surface.

20. A light emitting diode, comprising:

a light emitting structure including a light emitting layer arranged on at least part of a first semiconductor layer, and a second semiconductor layer arranged on the light emitting layer, wherein the light emitting structure has a surface distal from the first semiconductor layer in a vertical direction and having a first region and a second region;

a first metal layer arranged on at least part of the first semiconductor layer and in contact with the first semiconductor layer;

a second metal layer arranged over at least of the second semiconductor layer and electrically coupled with the second semiconductor layer; and

an electrode layer arranged over the surface and including a first region electrode layer and a second region electrode layer,

wherein

the first region electrode layer is arranged on the first region of the surface and the second region electrode layer arranged on the second region of the surface; and

the electrode layer has a bonding regions available for bonding with a package substrate, and the bonding region is not overlapped with the first metal layer or the second metal layer in a vertical direction.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2023
From: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
To: QUANZHOU SANAN SEMICONDUCTOR TECHNOLOGY CO., LTD.
Reel/Frame 065302/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2020
From: PENG, KANGWEI; LIN, XIAOXIONG; HE, ANHE; LIN, SUHUI; ZHENG, JIANSEN; HSU, CHENKE
To: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 054782/0559 →
Priority Claims (1)
CN 201510655970.X · Oct 13, 2015 · national
Continuity (5)
Continuation 16900538 · Jun 12, 2020
Continuation 16409090 · May 10, 2019
Continuation 15853845 · Dec 24, 2017
Continuation PCTCN2016097758 · Sep 1, 2016
Related Publication 20210126176A1 · Apr 29, 2021