Semiconductor memory device
According to one embodiment, a semiconductor memory device includes first to nth string units (n being a natural number of 3 or more), a plurality of layers of word lines, and (n−1) layers of select gate layers. The first to nth string units each includes a memory string. The memory string includes a plurality of memory cells and a plurality of select transistors connected in series in a first direction. The (n−1) layers of select gate layers include first to (2×(n−1))th select gates electrically isolated from each other. The first string unit is selected by the first to (n−1)th select gates. The kth string unit (k being not less than 1 and not more than n) is selected by the kth to (n+k−2)th select gates. The nth string unit is selected by the nth to (2×(n−1))th select gates.
1. A semiconductor memory device, comprising first to nth memory cells, n being a natural number, the first to nth memory cells each having a plurality of thresholds,
the first to nth memory cells being selected simultaneously in a read operation,
after the read operation, k pieces of read data, k being n or less, being determined from n pieces of data read from the first to nth memory cells, wherein
the first to nth memory cells are each provided in first to nth memory strings.
2. The device according to claim 1 , wherein
the first to nth memory cells include a first state, a second state, a third state, and an hth state, h being 3 or more,
the first state and the second state are discriminated by applying a first read voltage to gates of the first to nth memory cells,
the second state and the third state are discriminated by applying a second read voltage to the gates of the first to nth memory cells,
the (h-l)th state and the hth state are discriminated by applying th read voltage to the gates of the first to nth memory cells, and
a voltage of the first to (h- 1 )th read voltages is applied to the first to nth memory cells in the read operation.
3. The device according to claim 1 , wherein
first to nth word lines are each connected to the first to nth memory cells, and
first to nth voltages are each applied to the first to nth word lines.
4. The device according to claim 3 , wherein
first to nth bit lines are each connected to the first to nth memory strings, and
first to nth sense amplifiers are each connected to the first to nth bit lines.
5. The device according to claim 1 , wherein the n is 3, and the k is 3.
6. A semiconductor memory device, comprising a first memory cell and a second memory cell, the first memory cell and the second memory cell each having a plurality of thresholds,
the first memory cell and the second memory cell being selected simultaneously in a read operation,
after the read operation, one piece of read data is determined from first data read from the first memory cell and second data read from the second memory cell.
7. The device according to claim 6 , wherein
the first memory cell and the second memory cell each include a first state, a second state, and a third state,
the first state and the second state are discriminated by applying a first read voltage to a gate of the first memory cell and a gate of the second memory cell,
the second state and the third state are discriminated by applying a second read voltage to the gate of the first memory cell and the gate of the second memory cell,
first read operation is performed by applying the first read voltage to the first memory cell and applying the first read voltage to the second memory cell,
second read operation is performed by applying the first read voltage to the first memory cell and applying the second read voltage to the second memory cell, and
third read operation is performed by applying the second read voltage to the first memory cell and applying the first read voltage to the second memory cell.
8. The device according to claim 6 , wherein
the first memory cell is provided in a first memory string, and
the second memory cell is provided in a second memory string.
9. The device according to claim 8 , wherein
a first word line is connected to the first memory cell,
a second word line is connected to the second memory cell, and
a first voltage is applied to the first word line and a second voltage is applied to the second word line.
10. The device according to claim 9 , wherein
a first bit line is connected to the first memory string,
a second bit line is connected to the second memory string,
a first sense amplifier is connected to the first bit line, and
a second sense amplifier is connected to the second bit line.
11. A semiconductor memory device, comprising first to nth memory cells, n being a natural number, the first to nth memory cells each having a plurality of thresholds,
the first to nth memory cells being selected simultaneously in a read operation,
after the read operation, k pieces of read data, k being n or less, being determined from n pieces of data read from the first to nth memory cells, wherein
the n is 3, and the k is 3.
12. The device according to claim 11 , wherein
the first to nth memory cells include a first state; a second state, a third state; and an hth state, h being 3 or more,
the first state and the second state are discriminated by applying a first read voltage to gates of the first to nth memory cells,
the second state and the third state are discriminated by applying a second read voltage to the gates of the first to nth memory cells,
the (h- 1 )th state and the hth state are discriminated by applying an (h- 1 )th read voltage to the gates of the first to nth memory cells, and
a voltage of the first to (h- 1 )th read voltages is applied to the first to nth memory cells in the read operation.
13. The device according to claim 11 , wherein
first to nth word lines are each connected to the first to nth memory cells, and
first to nth voltages are each applied to the first to nth word lines.
14. The device according to claim 13 , wherein
first to nth hit lines are each connected to the first to nth memory strings, and
first to nth sense amplifiers are each connected to the first to nth bit lines.