Semiconductor device having stepped multi-stack transistor structure
A semiconductor device include: a substrate; a 1 st transistor formed above the substrate, the 1 st transistor including a 1 st channel set of a plurality of 1 st nanosheet layers, a 1 st gate structure surrounding the 1 st nanosheet layers, and 1 st and 2 nd source/drain regions at both ends of the 1 st channel set; and a 2 nd transistor formed above the 1 st transistor in a vertical direction, the 2 nd transistor including a 2 nd channel set of a plurality of 2 nd nanosheet layers, a 2 nd gate structure surrounding the 2 nd nanosheet layers, and 3 rd and 4 th source/drain regions at both ends of the 2 nd channel set, wherein the 1 st channel set has a greater width than the 2 nd channel set, wherein a number of the 1 st nanosheet layers is smaller than a number of the 2 nd nanosheet layers, and wherein a sum of effective channel widths of the 1 st nanosheet layers is substantially equal to a sum of effective channel width of the 2 nd nanosheet layers.
1. A semiconductor device comprising:
a substrate;
a 1 st transistor formed above the substrate, the 1 st transistor comprising a 1 st channel set of a plurality of 1 st nanosheet layers, a 1 st gate structure surrounding the 1 st nanosheet layers, and 1 st and 2 nd source/drain regions at both ends of the 1 st channel set; and
a 2 nd transistor formed above the 1 st transistor in a vertical direction, the 2 nd transistor comprising a 2 nd channel set of a plurality of 2 nd nanosheet layers, a 2 nd gate structure surrounding the 2 nd nanosheet layers, and 3 rd and 4 th source/drain regions at both ends of the 2 nd channel set;
wherein the 2 nd source/drain region has a greater width than the 4 th source/drain region in a channel width direction so that the 4 th source/drain region vertically overlaps only a part of the 2 nd source/drain region, the channel width direction being perpendicular to a channel length direction in which the 1 st and 2 nd source/drain regions are connected though the 1 st channel set and the 3 rd and 4 th source/drain regions are connected though the 2 nd channel set,
wherein the semiconductor device further comprises a source/drain contact structure connected to the 2 nd source/drain region through a space where the 4 th source/drain region does not vertically overlap the 2 nd source/drain region.
2. The semiconductor device of claim 1 , wherein the source/drain contact structure laterally contacts a side surface of the 4 th source/drain region and contacts a top surface of the 2 nd source/drain region.
3. The semiconductor device of claim 1 , wherein the 1 st nanosheet layers have a greater width than the 2 nd nanosheet layers, and
wherein the 2 nd channel set vertically overlaps only a part of the 1 st channel set.
4. The semiconductor device of claim 1 , wherein a width of a 2 nd nanosheet layer having a greatest width among the 2 nd nanosheet layers is smaller than a width of a 1 st nanosheet layer having a smallest width among the 1 st nanosheet layers.
5. The semiconductor device of claim 4 , wherein a number of the 2 nd nanosheet layers is greater than a number of the 1 st nanosheet layers.
6. The semiconductor device of claim 5 , further comprising:
a gate contact structure connected to at least the 2 nd gate structure;
a 1 st source/drain contact structure connected the 1 st source/drain region;
a 2 nd source/drain contact structure which is the source/drain contact structure connected to the 2 nd source/drain region through the space where the 4 th source/drain region does not vertically overlap the 2 nd source/drain region; and
a 3 rd source/drain contact structure connected to the 3 rd source/drain region, wherein the 2 nd source/drain contact structure laterally contacts a side surface of the 4 th source/drain region and contacts a top surface of the 2 nd source/drain region.
7. The semiconductor device of claim 6 , further comprising 1 st to 4 th metal patterns formed above the 2 nd transistor,
wherein the 1 st metal pattern is connected to the 1 st source/drain contact structure to provide one of a positive supply voltage and a negative supply voltage,
wherein the 2 nd metal pattern is connected to the 2 nd source/drain contact structure,
wherein the 3 rd metal pattern is connected to the gate contact structure, and
wherein the 4 th metal pattern is connected to the 3 rd source/drain contact structure to provide the other of the positive supply voltage and the negative supply voltage.
8. The semiconductor device of claim 6 , further comprising a 1 st metal pattern buried in the substrate, and 2 nd , 3 rd and 4 th metal patterns formed above the 2 nd transistor,
wherein the 1 st metal pattern is connected to the 1 st source/drain contact structure to provide one of a positive supply voltage and a negative supply voltage,
wherein the 2 nd metal pattern is connected to the 2 nd source/drain contact structure,
wherein the 3 rd metal pattern is connected to the gate contact structure, and
wherein the 4 th metal pattern is connected to the 3 rd source/drain contact structure to provide the other of the positive supply voltage and the negative supply voltage.
9. A semiconductor device comprising:
a substrate;
a 1 st transistor formed above the substrate, the 1 st transistor comprising a 1 st channel set of a plurality of 1 st nanosheet layers, a 1 st gate structure surrounding the 1 st nanosheet layers, and 1 st and 2 nd source/drain regions at both ends of the 1 st channel set; and
a 2 nd transistor formed above the 1 st transistor in a vertical direction, the 2 nd transistor comprising a 2 nd channel set of a plurality of 2 nd nanosheet layers, a 2 nd gate structure surrounding the 2 nd nanosheet layers, and 3 rd and 4 th source/drain regions at both ends of the 2 nd channel set,
wherein the 1 st channel set has a greater width than the 2 nd channel set,
wherein a number of the 1 st nanosheet layers is smaller than a number of the 2 nd nanosheet layers, and
wherein a sum of effective channel widths of the 1 st nanosheet layers is substantially equal to a sum of effective channel width of the 2 nd nanosheet layers.
10. The semiconductor device of claim 9 , wherein the 2 nd channel set vertically overlaps only a part of the 1 st channel set.
11. The semiconductor device of claim 10 , wherein the 2 nd source/drain region has a greater width than the 4 th source/drain region so that the 4 th source/drain region vertically overlaps only a part of the 2 nd source/drain region.
12. The semiconductor device of claim 11 , wherein the 1 st source/drain region has a greater width than the 3 rd source/drain region.
13. The semiconductor device of claim 11 , further comprising a source/drain contact structure connected to the 2 nd source/drain region through a space where the 4 th source/drain region does not vertically overlap the 2 nd source/drain region.
14. The semiconductor device of claim 13 , further comprising:
a gate contact structure connected to at least the 1 st gate structure;
a 1 st source/drain contact structure connected the 1 st source/drain region;
a 2 nd source/drain contact structure which is the source/drain contact structure connected to the 2 nd source/drain region through the space where the 4 th source/drain region does not vertically overlap the 2 nd source/drain region; and
a 3 rd source/drain contact structure connected to the 3 rd source/drain region,
wherein the 2 nd source/drain contact structure laterally contacts a side surface of the 4 th source/drain region and contacts a top surface of the 2 nd source/drain region.
15. The semiconductor device of claim 14 , wherein a number of the 2 nd nanosheet layers is greater than a number of the 1 st nanosheet layers.
16. The semiconductor device of claim 15 , further comprising 1 st to 4 th metal patterns formed above the 2 nd transistor, wherein the 1 st metal pattern is connected to the 1 st source/drain contact structure to provide one of a positive supply voltage and a negative supply voltage,
wherein the 2 nd metal pattern is connected to the 2 nd source/drain contact structure
wherein the 3 rd metal pattern is connected to the gate structure, and
wherein the 5 th metal pattern is connected to the 3 rd source/drain contact structure to provide the other of the positive supply voltage and the negative supply voltage.
17. The semiconductor device of claim 15 , further comprising a 1 st metal pattern buried in the substrate, and 2 nd , 3 rd and to 4 th metal patterns formed above the 2 nd transistor,
wherein the 1 st metal pattern is connected to the 1 st source/drain contact structure to provide one of a positive supply voltage and a negative supply voltage,
wherein the 2 nd metal pattern is connected to the 2 nd source/drain contact structure,
wherein the 3 rd metal pattern is connected to the gate structure, and
wherein the 4 th metal pattern is connected to the 3 rd source/drain contact structure to provide the other of the positive supply voltage and the negative supply voltage.
18. A semiconductor device comprising:
a substrate;
a 1 st transistor formed above the substrate, the 1 st transistor comprising at least two 1 st channel layers and 1 st and 2 nd source/drain regions; and
a 2 nd transistor stacked above the 1 st transistor in a vertical direction, the 2 nd transistor comprising at least two 2 nd channel layers and 3 rd and 4 th source/drain regions;
wherein the 2 nd source/drain region is partially overlapped by the 4 th source/drain region in a vertical direction,
wherein at least one of the two 1 st channel layers is not vertically overlapped by any one of the 2 nd channel layers, and
wherein the semiconductor device further comprises a source/drain contact structure connected to the 2 nd source/drain region through a space where the 4 th source/drain region does not overlap the 2 nd source/drain region in the vertical direction.
19. The semiconductor device of claim 18 , wherein the 1 st channel layers are nanosheet channels, and the 2 nd channel layers are finFET channel layers.
20. The semiconductor device claim 18 , wherein a sum of effective channel widths of the 1 st channel layers is substantially equal to a sum of effective channel width of the 2 nd channel layers.