3D semiconductor device and structure with memory
A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors and a first metal layer, where the first transistors include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level is above the first level, and where the third level is above the second level; a second metal layer above the third level; and a third metal layer above the second metal layer, where the second transistors are aligned to the first transistors with less than 140 nm alignment error, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters.
1. A 3D semiconductor device, the device comprising:
a first level comprising a plurality of first single: crystal transistors;
a plurality of memory control circuits formed from at least a portion of said plurality of first single-crystal transistors;
a first metal layer disposed atop said plurality of first single-crystal transistors;
a second level comprising a plurality of second transistors;
a third level comprising a plurality of third transistors;
wherein said second level is above said first level, and
wherein said third level is above said second level;
a second metal layer above said third level; and
a third metal layer above said second metal layer,
wherein said plurality of second transistors are aligned to said plurality of first single crystal transistors with less than 140 nm and greater than about 2 nm of alignment error;
wherein said third metal comprises bit lines,
wherein said second level comprises a plurality of first memory cells,
wherein said third level comprises a plurality of second memory cells,
wherein one of said plurality of second transistors is at least partially self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step,
wherein each of said plurality of second memory cells comprises at least one of said plurality of third transistors,
wherein at least one of said plurality of second transistors is disposed at least partially atop at least a portion of said memory control circuits, and
wherein at least one of said memory control circuits controls operation of at least one of said plurality of first memory cells.
2. The 3D semiconductor device according to claim 1 , further comprising:
a connective path between said plurality of second transistors and said plurality of first single crystal transistors,
wherein said path comprises a through-layer via (TLV), and
wherein said through-layer via has a diameter less than 400 nm.
3. The 3D semiconductor device according to claim 1 ,
wherein fabrication processing of said device comprises first processing said first single crystal transistors followed by processing said second transistors and then processing said third transistors, and
wherein said first processing said first transistors accounts for a temperature and time associated with processing said second transistors and said third transistors by adjusting a process thermal budget of said first transistors accordingly.
4. The 3D semiconductor device according to claim 1 ,
wherein a memory array comprises a portion of or all of said plurality of first memory cells,
wherein a memory location or plurality of memory locations within said memory array comprise device specific process parameter data, and
wherein said memory array comprises FB-RAM cells.
5. The 3D semiconductor device according to claim 1 , further comprising:
an upper level above said third metal layer,
wherein said upper level comprises a mono-crystalline silicon layer.
6. The 3D semiconductor device according to claim 1 , further comprising:
a first set of external connections beneath said first level to connect said device to a first external device,
wherein said first set of external connections comprises through vias.
7. The 3D semiconductor device according to claim 1 ,
wherein at least one of said plurality of second transistors is above at least a portion of said first metal layer.
8. The 3D semiconductor device according to claim 1 ,
wherein said memory control circuits control a magnitude, duration, and repetition rate of memory write voltages delivered to said plurality of first memory cells and to said plurality of second memory cells by using a distance between a write driver circuit and an associated memory cell.
9. The 3D semiconductor device according to claim 1 ,
wherein said memory control circuits control a magnitude, duration, and repetition rate of memory write voltages by using one or more temperatures at which said 3D semiconductor device is operating.
10. A 3D semiconductor device, the device comprising:
a first level comprising both a plurality of first single-crystal transistors and a first metal layer, said first metal layer disposed atop said plurality of first single-crystal transistors;
a plurality of memory control circuits formed from at least a portion of said plurality of first single-crystal transistors;
a second level comprising a plurality of second transistors;
a third level comprising a plurality of third transistors;
wherein said second level is above said first level, and
wherein said third level is above said second level;
a second metal layer above said third level;
a third metal layer above said second metal layer;
wherein said second transistors are aligned to said first transistors with less than 140 nm and greater than about 2 nm of alignment error,
wherein said third metal comprises bit lines,
wherein said second level comprises a plurality of first memory cells,
wherein said third level comprises a plurality of second memory cells,
wherein one of said plurality of second transistors is at least partially self-aligned to at least one of said plurality of third transistors being processed following a same lithography step,
wherein at least one of said plurality of second transistors is disposed at least partially atop at least a portion of said memory control circuits,
wherein each of said plurality of second memory cells comprises at least one of said plurality of third transistors; and
an upper level disposed above said third metal layer;
wherein said upper level comprises a mono-crystalline silicon layer.
11. The 3D semiconductor device according to claim 10 , further comprising:
a connective path between said plurality of second transistors and said plurality of first single: crystal transistors;
wherein said path comprises a through-layer via (TLV), and
wherein said TLV has a diameter less than 400 nm.
12. The 3D semiconductor device according to claim 10 ,
wherein at least one of said plurality of second transistors comprises polysilicon.
13. The 3D semiconductor device according to claim 10 ,
wherein a memory array comprises a portion of or all of said plurality of first memory cells,
wherein a memory location, or plurality of memory locations, within said memory array comprise device-specific process parameter data, and
wherein said memory array comprises FB-RAM cells.
14. The 3D semiconductor device according to claim 10 , further comprising:
at least one TSV (Through Silicon Via) through said mono-crystalline layer to provide connections to an external device.
15. The 3D semiconductor device according to claim 10 ,
wherein at least one of said plurality of second transistors is at least partially above at least one of said plurality of first single-crystal transistors.
16. The 3D semiconductor device according to claim 10 , further comprising:
a first set of external connections disposed beneath said first level that connects said device to a first external device; and
a second set of external connections disposed atop said second metal layer that connects said device to a second external device.
17. A 3D semiconductor device, the device comprising:
a first level comprising both a plurality of first single: crystal transistors and a first metal layer;
a plurality of memory control circuits formed from at least a portion of said plurality of first single-crystal transistors;
wherein said first metal layer is disposed atop said plurality of first single-crystal transistors;
a second level comprising a plurality of second transistors;
a third level comprising a plurality of third transistors;
wherein said second level is above said first level, and
wherein said third level is above said second level;
a second metal layer above said third level; and
a third metal layer above said second metal layer,
wherein said second transistors are aligned to said first transistors with less than 140 nm and greater than about 2 nm of alignment error,
wherein said second level comprises a plurality of first memory cells,
wherein said third level comprises a plurality of second memory cells,
wherein said memory control circuits control a magnitude and a duration of memory write voltages delivered to said plurality of first memory cells and to said plurality of second memory cells by using a distance between a write driver circuit and an associated memory cell, and
wherein said memory control circuits additionally control memory write voltages by using one or more temperatures at which said 3D semiconductor device is operating, as determined by monitoring charge loss rates in one or more reference cells; whereon said one or more temperatures are determined by using one or more reference cells and by monitoring charge loss rates in said reference cells.
18. The 3D semiconductor device according to claim 17 , further comprising at least one TSV (Through Silicon Via) through at least a part of said first level to provide connections to an external device.
19. The 3D semiconductor device according to claim 17 ,
wherein at least one of said plurality of third transistors is a junction-less transistor;
wherein each of said junction-less transistors (JLT) comprise a JLT channel, a JLT drain, and a JLT source, and
wherein said JLT channel, said JLT drain, and said JLT source comprise a same dopant type.
20. The 3D semiconductor device according to claim 17 ,
wherein one of said plurality of second transistors is at least partially self-aligned to at least one of said plurality of third transistors being processed following a same lithography step.
21. The 3D semiconductor device according to claim 17 , further comprising:
an upper level above said third metal layer;
wherein said upper level comprises a mono-crystalline silicon layer.
22. The 3D semiconductor device according to claim 17 , further comprising:
a connective path between said plurality of second transistors and said plurality of first single: crystal transistors,
wherein said path comprises a through-layer via (TLV), and
wherein said TLV has a diameter less than 400 nm.