Method for fabricating a semiconductor device having a trench exposing a sidewall of the contact plug aligned with the sidewall of the substrate
A method including forming an inter-layer insulation layer on a substrate, forming a plug material penetrating the inter-layer insulation layer and contacting a portion of the substrate, forming a contact plug by etching the plug material, forming a trench exposing a side wall of the contact plug by etching the substrate and the inter-layer insulation layer to be aligned with a side wall of the contact plug, forming a gate insulation layer on a surface of the trench and the exposed side wall of the contact plug, and forming a gate electrode partially filling the trench on the gate insulation layer. The method includes an inter-layer insulation layer formed on a substrate, a contact plug penetrating the inter-layer insulation layer and contacting a portion of the substrate, trenches extending in a line shape and aligned with side walls of the contact plug, and a plug spacer positioned between the trenches and surrounding the contact plug.
1. A method for manufacturing a semiconductor device, the method comprising:
forming a contact hole in a substrate;
filling the contact hole with a plug material;
forming a contact plug by etching the plug material;
forming a trench exposing a side wall of the contact plug by etching the substrate to be aligned with a side wall of the contact plug;
forming a gate insulation layer on the exposed side wall of the contact plug and a surface of the trench; and
forming a gate electrode on the gate insulation layer, the gate electrode partially filling the trench.
2. The method of claim 1 , further comprising:
before filling the contact hole with the plug material,
forming a preliminary spacer covering the side wall of the contact hole; and
further recessing the substrate exposed in the contact hole using the preliminary spacer.
3. The method of claim 2 , wherein forming the trench includes forming a plug spacer covering a non-exposed side wall of the contact plug by cutting the preliminary spacer.
4. The method of claim 3 , wherein the plug spacer further includes a bottom spacer positioned between the trench and a bottom edge of the contact plug.
5. The method of claim 4 , wherein the bottom spacer has a shape surrounding a lower outer wall of the contact plug.
6. The method of claim 1 , wherein forming the contact plug and forming the trench are simultaneously performed using one line-type mask.
7. The method of claim 1 , wherein the trench includes a pair of line-type trenches, and wherein
the pair of line-type trenches are self-aligned with the exposed side wall of the contact plug.
8. The method of claim 1 , wherein forming the contact hole includes:
forming an inter-layer insulation layer on the substrate;
forming an etch mask on the inter-layer insulation layer; and
etching the inter-layer insulation layer and the substrate using the etch mask.
9. The method of claim 1 , further comprising:
before forming the contact hole in the substrate, forming an element isolation layer defining an active area in the substrate, wherein the trench has a line shape crossing the active area and the element isolation layer.
10. The method of claim 1 , wherein a bottom surface of the trench is at a lower level than a bottom surface of the contact plug.
11. The method of claim 1 , wherein the gate insulation layer is formed by oxidating the exposed side wall of the contact plug and a surface of the trench.
12. The method of claim 1 , wherein a top portion of the contact plug is identical in width to a bottom portion of the contact plug.
13. The method of claim 1 , wherein a top portion of the contact plug is larger in width than a bottom portion of the contact plug.
14. The method of claim 1 , wherein the exposed side wall of the contact plug has a straight profile, and wherein the non-exposed side wall of the contact plug has a curved or round profile.
15. The method of claim 1 , wherein the plug material includes polysilicon.
16. The method of claim 1 , wherein a top surface of the gate electrode is at a lower level than a bottom surface of the contact plug.
17. A method for manufacturing a semiconductor device, the method comprising:
forming a contact hole in a substrate;
forming a plug material filling the contact hole;
forming a bit line contact plug by etching the plug material;
forming a gate trench exposing a side wall of the bit line contact plug by etching the substrate to be self-aligned with a side wall of the bit line contact plug;
forming a buried gate structure filling the gate trench; and
forming a bit line on the bit line contact plug.
18. The method of claim 17 , wherein forming the buried gate structure includes:
forming a gate insulation layer by oxidating the exposed side wall of the bit line contact plug and a surface of the gate trench; and
forming a buried gate electrode on the gate insulation layer so that the buried gate electrode partially fills the gate trench.
19. The method of claim 17 , further comprising:
before forming the plug material,
forming a preliminary spacer covering the side wall of the contact hole; and
further recessing the substrate exposed in the contact hole using the preliminary spacer, wherein forming the gate trench includes forming a plug spacer covering a non-exposed side wall of the bit line contact plug by cutting the preliminary spacer.
20. The method of claim 17 , wherein forming the contact hole includes:
forming an inter-layer insulation layer on the substrate;
forming an etch mask on the inter-layer insulation layer; and
etching the inter-layer insulation layer and the substrate using the etch mask.