IP Library Granted Patent US 12,419,043
Granted Patent B2
US 12,419,043 · App. 17/948,918 · Granted Sep 16, 2025

Semiconductor structure and method for manufacturing same

Inventor: Yizhi Zeng (Hefei, CN)
Assignee: CHANGXIN MEMORY TECHNOLOGIES., INC.
H10B12/50H10B12/09
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Quick Facts
Patent No.
US 12,419,043
App. No.
17/948,918
Granted
Sep 16, 2025
Kind
B2
Abstract

Embodiments of the disclosure provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate, a first isolation trench located in the substrate, a first insulating layer covering a bottom surface and a lower part of a sidewall of the first isolation trench, a second insulating layer covering an upper part of the sidewall of the first isolation trench, and a third insulating layer at least partially located between the first insulating layer and the second insulating layer to isolate the first insulating layer from the second insulating layer.

Claims (39)

1. A semiconductor structure comprising:

a substrate, and a first isolation trench and a second isolation trench located in the substrate;

a first insulating layer covering a bottom surface and a lower part of a sidewall of the first isolation trench;

a first filling layer, filling a recess defined by the first insulating layer in the first isolation trench;

a fourth insulating layer located between an inner wall of the first isolation trench and the first insulating layer, and covering the bottom surface and the lower part of the sidewall of the first isolation trench;

a second insulating layer covering an upper part of the sidewall of the first isolation trench;

a third insulating layer at least partially located between the first insulating layer and the second insulating layer to isolate the first insulating layer from the second insulating layer, wherein the third insulating layer comprises a bottom layer and a sidewall layer, the bottom layer covers a top of the fourth insulating layer, a top of the first insulating layer and a top of the first filling layer, and the sidewall layer is located between the upper part of the sidewall of the first isolation trench and the second insulating layer; and

a second filling layer, filling a recess defined by the second insulating layer together with the bottom layer of the third insulating layer in the first isolation trench;

wherein the second isolation trench comprises a first sub-trench and a second sub-trench, and a width of the second sub-trench is greater than a width of the first sub-trench;

the fourth insulating layer covers a bottom surface and a lower part of a sidewall of the second sub-trench, and the first insulating layer fills a recess defined by the fourth insulating layer in the second sub-trench;

the third insulating layer covers an upper part of the sidewall of the second sub-trench and the top of the fourth insulating layer and the top of the first insulating layer; and

the second filling layer fills a recess defined by the third insulating layer in the second sub-trench.

2. The semiconductor structure of claim 1 , wherein a material of the first insulating layer and a material of the second insulating layer comprise nitride, and a material of the third insulating layer comprises oxide.

3. The semiconductor structure of claim 1 , wherein a ratio of a height of the first insulating layer to a height of the second insulating layer is in a range of 2 to 6, and a ratio of a height of a part of the third insulating layer located between the first insulating layer and the second insulating layer to the height of the second insulating layer is in a range of 0.3 to 0.7.

4. The semiconductor structure of claim 1 , wherein both a thickness of the first insulating layer and a thickness of the second insulating layer are in a range of 5 nm to 30 nm.

5. The semiconductor structure of claim 1 , wherein the first isolation trench is located in a device core region or a peripheral region for isolating selection transistors, and the second isolation trench is located in a device unit region for isolating memory units.

6. A method for manufacturing a semiconductor structure, comprising:

providing a substrate;

etching the substrate to form a first isolation trench and a second isolation trench, wherein the second isolation trench comprises a first sub-trench and a second sub-trench, and a width of the second sub-trench is greater than a width of the first sub-trench;

forming a first insulating layer, wherein the first insulating layer covers a bottom surface and a lower part of a sidewall of the first isolation trench;

forming a third insulating layer on the first insulating layer, wherein the third insulating layer at least covers a top of the first insulating layer; and

forming a second insulating layer on the third insulating layer, wherein the second insulating layer covers an upper part of the sidewall of the first insulating trench, and is isolated from first insulating layer by the third insulating layer;

wherein before forming the first insulating layer, the method further comprises:

forming a fourth insulating material layer, wherein the fourth insulating material layer covers an inner surface of the first isolation trench and an inner surface of the second sub-trench, and fills the first sub-trench.

7. The method of claim 6 , wherein the forming the first insulating layer comprises:

forming a first insulating material layer, wherein the first insulating material layer covers the fourth insulating material layer and fully fills the second sub-trench;

forming a first filling material layer, wherein the first filling material layer covers the first insulating material layer and fully fills the first isolation trench; and

etching the first filling material layer, the first insulating material layer and the fourth insulating material layer to make a top of the first insulating material layer, a top of the fourth insulating material layer and a top of the first filling material layer lower than an upper surface of the substrate, so as to form the first insulating layer, the fourth insulating layer and the first filling layer.

8. The method of claim 7 , wherein the forming the third insulating layer comprises:

forming and etching a third insulating material layer to form the third insulating layer covering a top of the fourth insulating layer, the top of the first insulating layer and a top of the first filling layer, and the upper part of the sidewall of the first isolation trench and the upper part of a sidewall of the second sub-trench,

wherein a part of the third insulating layer in the first isolation trench defines a first accommodating cavity, and a part of the third insulating layer in the second sub-trench defines a second accommodating cavity.

9. The method of claim 8 , wherein the forming the second insulating layer comprises:

forming a second insulating material layer, wherein the second insulating material layer covers a bottom surface and a sidewall of the first accommodating cavity and fully fills the second accommodating cavity; and

etching the second insulating material layer to remove the second insulating material layer located in the second accommodating cavity and the second insulating material layer covering the bottom surface of the first accommodating cavity, so as to form the second insulating layer covering the sidewall of the first accommodating cavity.

10. The method of claim 9 , after forming the second insulating layer, the method further comprises:

forming a second filling material layer on the third insulating layer and the second insulating layer, wherein the second filling material layer fully fills the first accommodating cavity and the second accommodating cavity; and

etching the second filling material layer to make a top of the second filling material layer flush with a top of the second insulating layer, so as to form a second filling layer.

11. The semiconductor structure of claim 1 , wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer.

12. The method of claim 6 , wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2022
From: ZENG, YIZHI
To: CHANGXIN MEMORY TECHNOLOGIES .,INC.
Reel/Frame 061787/0615 →
Priority Claims (1)
CN 202210726332.2 · Jun 23, 2022 · national
Continuity (2)
Continuation PCTCN2022105152 · Jul 12, 2022
Related Publication 20230017189A1 · Jan 19, 2023
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