IP Library Granted Patent US 11,239,273
Granted Patent B2
US 11,239,273 · App. 17/157,152 · Granted Feb 1, 2022

Imaging device and electronic device

Inventors: Takayuki Ikeda (Kanagawa, JP); Naoto Kusumoto (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/14634H01L27/1207H01L27/1225H01L27/1229H01L27/1469H01L27/14601H01L27/14616H01L27/14643H01L27/14689H01L27/14692H01L29/78H01L29/7869H01L2224/80895H01L2224/80896
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,239,273
App. No.
17/157,152
Granted
Feb 1, 2022
Kind
B2
Abstract

An imaging device having a three-dimensional integration structure is provided. A first structure including a transistor including silicon in an active layer or an active region and a second structure including an oxide semiconductor in an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second structures are bonded to each other; thus, an imaging device having a three-dimensional integration structure is formed.

Claims (34)

1. An imaging device comprising:

a first metal part and a second metal part in contact with each other, the second metal part provided below the first metal part;

a plurality of first transistors provided over the first metal part;

a photoelectric conversion element provided over the plurality of first transistors; and

a second transistor provided below the second metal part,

wherein the photoelectric conversion element is formed in a semiconductor substrate,

wherein a p-type region of the photoelectric conversion element is electrically connected to a conductive layer below the semiconductor substrate,

wherein a light-blocking layer provided over the semiconductor substrate overlaps a region where the p-type region is in electrical contact with the conductive layer,

wherein one of the plurality of first transistors shares a source or drain region of another of the plurality of first transistors,

wherein the source or drain region overlaps a joint region between the first metal part and the second metal part,

wherein the source or drain region serves as a floating diffusion (FD) node,

wherein a gate of at least one of the plurality of first transistors is electrically connected to a first wiring,

wherein an anode of the photoelectric conversion element is provided to face a light-receiving surface, and includes a depressed area, and

wherein the anode of the photoelectric conversion element is electrically connected to a second wiring provided on a same layer as the first wiring through the depressed area.

2. The imaging device according to claim 1 , wherein current characteristics of the second transistor is different from current characteristics of the plurality of first transistors.

3. The imaging device according to claim 1 , wherein the first metal part is a same metal element as the second metal part.

4. The imaging device according to claim 1 , wherein an off-state current per channel width of the plurality of first transistors is lower than an off-state current per channel width of the second transistor.

5. An imaging device comprising:

a first metal part and a second metal part in contact with each other, the second metal part provided below the first metal part;

a plurality of first transistors provided over the first metal part;

a photoelectric conversion element provided over the first metal part; and

a second transistor provided below the second metal part,

wherein the photoelectric conversion element is formed in a semiconductor substrate,

wherein a p-type region of the photoelectric conversion element is electrically connected to a conductive layer below the semiconductor substrate,

wherein a light-blocking layer provided over the semiconductor substrate overlaps a region where the p-type region is in electrical contact with the conductive layer,

wherein one of the plurality of first transistors shares a source or drain region of another of the plurality of first transistors,

wherein the source or drain region overlaps a joint region between the first metal part and the second metal part,

wherein the source or drain region serves as a floating diffusion (FD) node,

wherein a gate of at least one of the plurality of first transistors is electrically connected to a first wiring,

wherein an anode of the photoelectric conversion element is provided to face a light-receiving surface, and includes a depressed area, and

wherein the anode of the photoelectric conversion element is electrically connected to a second wiring provided on a same layer as the first wiring through the depressed area.

6. The imaging device according to claim 5 , wherein current characteristics of the second transistor is different from current characteristics of the plurality of first transistors.

7. The imaging device according to claim 5 , wherein the first metal part is a same metal element as the second metal part.

8. The imaging device according to claim 5 , wherein an off-state current per channel width of the plurality of first transistors is lower than an off-state current per channel width of the second transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2021
From: IKEDA, TAKAYUKI; KUSUMOTO, NAOTO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 055020/0028 →
Priority Claims (2)
JP 2015-256138 · Dec 28, 2015 · national
JP 2016-171454 · Sep 2, 2016 · national
Continuity (4)
Continuation 16541292 · Aug 15, 2019
Continuation 15947911 · Apr 9, 2018
Division 15383327 · Dec 19, 2016
Related Publication 20210143203A1 · May 13, 2021
Cited By (3)
US 12,396,181 US 12,439,581 US 12,659,621