Granted Patent B2

US 12,439,581 · App. 17/783,071 · Granted Oct 7, 2025

Inventors: Ryota Hodo (Atsugi, JP); Katsuaki Tochibayashi (Isehara, JP); Toshiya Endo (Atsugi, JP); Shunpei Yamazaki (Setagaya, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H10B12/00H10D30/6734H10D30/6755H10D86/423H10D86/481H10D86/60H10D87/00H10D99/00

Abstract

Claims (74)

1. A semiconductor device comprising:

a transistor comprising a gate electrode, a gate insulating film, a source electrode, and a drain electrode;

a first insulator over the transistor;

a second insulator over the first insulator;

a third insulator over the second insulator;

a first electrode in contact with a top surface of the source electrode; and

a second electrode in contact with a top surface of the drain electrode,

wherein the second insulator comprises a first opening portion overlapping with the source electrode and a second opening portion overlapping with the drain electrode,

wherein the third insulator is in contact with a side surface of the second insulator and a top surface and a side surface of the first insulator inside the first opening portion and the second opening portion,

wherein the first electrode is positioned through the first opening portion, and

wherein the second electrode is positioned through the second opening portion.

2. The semiconductor device according to claim 1 ,

wherein the first insulator comprises a first groove portion overlapping with the first opening portion and a second groove portion overlapping with the second opening portion.

3. The semiconductor device according to claim 2 ,

wherein a side surface of the first electrode is in contact with the third insulator in the first opening portion and the first groove portion, and

wherein a side surface of the second electrode is in contact with the third insulator in the second opening portion and the second groove portion.

4. The semiconductor device according to claim 2 , further comprising:

a fourth insulator provided in contact with a side surface of the first electrode; and

a fifth insulator provided in contact with a side surface of the second electrode,

wherein a side surface of the fourth insulator is in contact with the third insulator in the first opening portion and the first groove portion, and

wherein a side surface of the fifth insulator is in contact with the third insulator in the second opening portion and the second groove portion.

5. The semiconductor device according to claim 1 ,

wherein the second insulator comprises aluminum oxide.

6. The semiconductor device according to claim 1 ,

wherein the first insulator comprises silicon oxide, and

wherein the third insulator comprises silicon nitride.

7. The semiconductor device according to claim 1 ,

wherein the transistor comprises an oxide semiconductor layer, and

wherein the oxide semiconductor layer comprises any one or more selected from In, Ga, and Zn.

8. The semiconductor device according to claim 7 ,

wherein the gate insulating film, the source electrode, and the drain electrode are provided over the oxide semiconductor layer,

wherein the gate electrode is provided over the gate insulating film,

wherein an opening is formed in the first insulator to overlap with a region between the source electrode and the drain electrode, and

wherein the gate insulating film and the gate electrode are positioned in the opening.

9. The semiconductor device according to claim 8 , further comprising a sixth insulator covering the oxide semiconductor layer, the source electrode, and the drain electrode,

wherein an opening is formed in the sixth insulator to overlap with a region between the source electrode and the drain electrode, and

wherein the first insulator is provided over the sixth insulator.

10. The semiconductor device according to claim 9 ,

wherein the sixth insulator comprises silicon nitride.

11. The semiconductor device according to claim 1 ,

wherein the first insulator and the second insulator are formed into island shapes, and

wherein the third insulator covers the first insulator and the second insulator.

12. The semiconductor device according to claim 1 ,

wherein the second insulator comprises a third opening portion in a region not overlapping with the gate electrode, the source electrode, or the drain electrode, and

wherein the third insulator is in contact with the side surface of the second insulator and the top surface of the first insulator inside the third opening portion.

13. A method for manufacturing a semiconductor device, comprising the steps of:

forming a transistor comprising a source electrode and a drain electrode, and a first insulator above the source electrode and the drain electrode;

depositing a second insulator comprising aluminum oxide over the first insulator;

forming, in the second insulator, a first opening portion overlapping with the source electrode and a second opening portion overlapping with the drain electrode;

depositing a third insulator over the first insulator and the second insulator;

forming a fourth insulator over the third insulator to be embedded in regions overlapping with the first opening portion and the second opening portion; and

forming a third opening portion reaching the source electrode and a fourth opening portion reaching the drain electrode in the first insulator, the third insulator, and the fourth insulator,

wherein the third opening portion is positioned inside the first opening portion in a top view,

wherein the fourth opening portion is positioned inside the second opening portion in the top view, and

wherein a first electrode and a second electrode are formed in the third opening portion and the fourth opening portion, respectively.

14. The method for manufacturing a semiconductor device, according to claim 13 ,

wherein the first insulator and the fourth insulator each comprise silicon oxide, and

wherein the third insulator comprises silicon nitride.

15. The method for manufacturing a semiconductor device, according to claim 13 ,

wherein the third opening portion and the fourth opening portion are formed by a dry etching method using a gas comprising fluorine.

16. A method for manufacturing a semiconductor device, comprising the steps of:

depositing a second insulator over a first insulator;

depositing, over the second insulator, an oxide semiconductor layer comprising any one or more selected from In, Ga, and Zn;

processing the oxide semiconductor layer into an island shape by a dry etching method using a gas comprising methane and at least one of argon, nitrogen, and hydrogen; and

processing the second insulator into an island shape by a dry etching method using a gas comprising a halogen to expose a top surface of the first insulator.

17. The method for manufacturing a semiconductor device, according to claim 16 ,

wherein the first insulator comprises hafnium oxide, and

wherein the second insulator comprises silicon oxide.

18. The method for manufacturing a semiconductor device, according to claim 16 ,

wherein, after the second insulator is processed into the island shape, a third insulator is deposited to cover the first insulator, the second insulator, and the oxide semiconductor layer, and

wherein the third insulator comprises silicon nitride.

19. The method for manufacturing a semiconductor device, according to claim 16 ,

wherein before the step of processing the oxide semiconductor layer, a hard mask comprising tungsten, an organic coating film comprising a non-photosensitive organic resin and a resist mask are formed over the oxide semiconductor layer in order, and then

wherein the oxide semiconductor layer is processed into the island shape using the hard mask.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (52)