Dynamic sense node voltage to compensate for variances when sensing threshold voltages of memory cells
Technology for sensing non-volatile memory cells in which one or more sense nodes are charged to a sense voltage having a magnitude that improves sensing accuracy. One sense node may be charged to different sense voltages when sensing different memory cells at different times. Multiple sense nodes may be charged to a corresponding multiple different sense voltages when sensing different memory cells at the same time. The one or more sense nodes are allowed to discharge based on respective currents of memory cells for a pre-determined time while applying a reference voltage to the memory cells. The Vts of the selected memory cells are assessed based on respective voltages on the one or more of sense nodes after the pre-determined time. Different sensing voltages may be used based on bit line voltage, bit line resistance, distance of memory cells from the sense node, or other factors.
1. An apparatus comprising:
a control circuit configured to connect to non-volatile memory cells, the control circuit further configured to connect to sense nodes associated with the memory cells, wherein the control circuit is configured to:
charge one or more of the sense nodes to different sense voltages having corresponding different magnitudes, including charging a first sense node of the one or more sense nodes to a sense voltage having a magnitude that depends inversely on distance between the first sense node and each respective selected memory cell;
allow the one or more sense nodes to discharge based on respective currents of selected memory cells for a pre-determined time while applying a reference voltage to the selected memory cells; and
determine whether threshold voltages of the selected memory cells are above or below a target threshold voltage associated with the reference voltage based on respective voltages on the one or more of sense nodes after the pre-determined time.
2. The apparatus of claim 1 , wherein:
the non-volatile memory cells are arranged in blocks; and
the control circuit is configured to charge the first sense node to a sense voltage having a magnitude that depends on a location of a block in which a selected memory cell resides.
3. The apparatus of claim 1 , wherein the control circuit is further configured to charge two or more of the sense nodes to a sense voltage having a magnitude that depends on resistances of respective bit lines associated with the selected memory cells.
4. The apparatus of claim 3 , wherein the control circuit is configured to vary the magnitude of the sense voltages on the two or more sense nodes inversely with the resistances of the respective bit lines.
5. The apparatus of claim 1 , wherein the apparatus further comprises:
a memory structure die comprising the non-volatile memory cells, wherein the non-volatile memory cells are arranged in blocks; and
a control die comprising the control circuit and sense amplifiers, wherein each sense amplifier comprises a sense node, wherein the control circuit is configured to:
charge the first sense node in a first sense amplifier of the sense amplifiers to a first sense voltage having a first magnitude;
connect a first selected memory cell in a first block to the first sense node while applying the reference voltage to the first selected memory cell to allow a current of the first selected memory cell to discharge the first sense node for the pre-determined time, wherein the first block has a first distance to the first sense amplifier;
determine whether a threshold voltage of the first selected memory cell is greater than the target threshold voltage based on a voltage on the first sense node after the sense node has discharged for the pre-determined time;
charge the first sense node in the first sense amplifier to a second sense voltage having a second magnitude that is less than the first magnitude;
connect a second selected memory cell in a second block to the first sense node while applying the reference voltage to the second selected memory cell to allow a current of the second selected memory cell to discharge the first sense node for the pre-determined time, wherein the second block has a second distance to the first sense amplifier that is greater than the first distance; and
determine whether a threshold voltage of the second selected memory cell is greater than the target threshold voltage based on a voltage on the first sense node after the sense node has discharged for the pre-determined time.
6. The apparatus of claim 1 , wherein the apparatus further comprises:
a memory structure die comprising the non-volatile memory cells, wherein the memory structure die further comprises bit lines associated with the non-volatile memory cells; and
a control die comprising the control circuit and sense amplifiers, wherein each the sense amplifier comprises a sense node and is associated with one of the bit lines, wherein the control circuit is further configured to:
charge a second sense node in a first sense amplifier of the sense amplifiers to a second sense voltage having a first magnitude;
connect a first selected memory cell associated with a first bit line to the second sense node while applying the reference voltage to the first selected memory cell to allow a current of the first selected memory cell to discharge the second sense node for the pre-determined time;
determine whether a threshold voltage of the first selected memory cell is greater than the target threshold voltage based on a voltage on the second first sense node after the second sense node has discharged for the pre-determined time;
charge a third sense node in a second sense amplifier of the sense amplifiers to a second sense voltage having a second magnitude that is lower than the first magnitude;
connect a second selected memory cell associated with a second bit line to the third sense node while applying the reference voltage to the second selected memory cell to allow a current of the second selected memory cell to discharge the third sense node for the pre-determined time, wherein the second bit line has a greater resistance than the first bit line; and
determine whether a threshold voltage of the second selected memory cell is greater than the target threshold voltage based on a voltage on the second sense node after the second sense node has discharged for the pre-determined time.
7. The apparatus of claim 1 , wherein:
the non-volatile memory cells are arranged as NAND strings;
the NAND strings are connected to bit lines; and
the control circuit is further configured to:
charge bit lines associated with the selected memory cells to bit line voltages; and
charge the one or more sense nodes to sense voltages that compensate for differences in the bit line voltages at the NAND strings when the selected memory cells are being sensed.
8. A method of operating non-volatile storage, the method comprising:
charging a sense node in a sense amplifier to a first voltage;
connecting a first selected memory cell in a first block to the sense node while applying a voltage having a reference magnitude to the first selected memory cell to allow a current of the first selected memory cell to discharge the sense node for a pre-determined time;
determining whether the first selected memory cell has a threshold voltage greater than a target threshold voltage associated with the reference magnitude based on a voltage on the sense node after the sense node has discharged for the pre-determined time;
charging the sense node to a second voltage having a different magnitude from the first voltage;
connecting a second selected memory cell in a second block to the sense node while applying a voltage having the reference magnitude to the second selected memory cell to allow a current of the second selected memory cell to discharge the sense node for the pre-determined time; and
determining whether the second selected memory cell has a threshold voltage greater than the target threshold voltage based on a voltage on the sense node after the sense node has discharged for the pre-determined time.
9. The method of claim 8 , further comprising:
determining a magnitude for the first voltage based on a first distance between the sense node and the first block; and
determining a magnitude for the second voltage based on a second distance between the sense node and the second block.
10. The method of claim 9 , further comprising:
determining that the first voltage is smaller than the second voltage in response to the second distance being longer than the first distance.
11. The method of claim 9 , further comprising:
determining that the first voltage is smaller than the second voltage in response to a first distance along a bit line between the first block and the sense node being greater than a second distance along the bit line between the second block and the sense node.
12. A non-volatile storage system, comprising:
a plurality of word lines;
a plurality of bit lines;
NAND strings comprising non-volatile memory cells, the non-volatile memory cells associated with the plurality of word lines, each NAND string associated with a bit line of the plurality of bit lines;
a plurality of sense amplifiers, each sense amplifier having a sense node, each sense amplifier associated with a bit line of the plurality of bit lines; and
a control circuit that:
charges selected bit lines associated with selected memory cells to bit line voltages;
charges two or more sense nodes to respective sense voltages that compensate for differences in the bit line voltages at respective NAND strings when selected memory cells of the respective NAND strings are connected to the two or more sense nodes, wherein the control circuit is configured to charge the two or more sense nodes to a sense voltage having a magnitude that depends on resistances of respective bit lines associated with the selected memory cells, wherein the control circuit is configured to vary the magnitude of the sense voltages on the two or more sense nodes inversely with the resistances of the respective bit lines;
connects the selected memory cells to the two or more sense nodes while applying a reference voltage to the selected memory cells to allow a current of the selected memory cells to discharge the two or more sense nodes for a pre-determined time; and
determines whether respective threshold voltages of the selected memory cells are greater than a target threshold voltage associated with the reference voltage based on a voltage on the two or more sense nodes after the two or more sense nodes has discharged for the pre-determined time.
13. The non-volatile storage system of claim 12 , wherein the control circuit further charges a first sense node to respective sense voltages that compensate for differences in the bit line voltages at the NAND strings due to different distances between the first sense node and the respective NAND strings.
14. The non-volatile storage system of claim 13 , wherein the control circuit further varies a magnitude of the sense voltage on the first sense node inversely with distance between the first sense node and the respective NAND strings.
15. The non-volatile storage system of claim 12 , wherein:
a first bit line of the respective bit lines has a first resistance between a first sense node of the two or more sense nodes and a first NAND string of the respective NAND strings;
a second bit line of the respective bit lines has a second resistance between a second sense node of the two or more sense nodes and a second NAND string of the respective NAND strings; and
the control circuit charges the first sense node and the second sense node to different sense voltages to compensate for the first resistance being different than the second resistance.
16. The non-volatile storage system of claim 15 , wherein the control circuit charges the first sense node to a greater sense voltage than the second sense node due to the second resistance being greater than the first resistance.
17. The non-volatile storage system of claim 15 , wherein the first NAND string and the second NAND string are in the same block of non-volatile memory cells.
18. The non-volatile storage system of claim 15 , wherein the first NAND string and the second NAND string are in different blocks of non-volatile memory cells.