Semiconductor device with reduced via resistance
A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided.
1. A method comprising:
forming a metal capping layer over a metal line disposed in a first dielectric layer;
forming a dielectric capping layer on the metal capping layer, at least a first portion of the dielectric capping layer being non-overlapping with the metal capping layer;
polishing the dielectric capping layer to expose the metal capping layer such that a top surface of an exposed portion of the metal capping layer is substantially co-planar with a top surface of the dielectric capping layer; and
depositing a second dielectric layer on the top surface of the exposed portion of the metal capping layer.
2. The method of claim 1 , wherein forming the metal capping layer comprises selectively depositing the metal capping layer over the metal line.
3. The method of claim 1 , wherein the metal capping layer comprises at least one of Co or Ru.
4. The method of claim 1 , wherein the metal capping layer comprises Rh.
5. The method of claim 1 , wherein the metal capping layer comprises at least one of W or P.
6. The method of claim 1 , wherein the dielectric capping layer comprises C.
7. The method of claim 6 , wherein after polishing the dielectric capping layer, the metal capping layer and the dielectric capping layer have a thickness between 15 nm and 55 nm.
8. The method of claim 1 , wherein after polishing the dielectric capping layer, the metal capping layer and the dielectric capping layer have a thickness between 25 nm and 45 nm.
9. The method of claim 8 , further comprising etching the second dielectric layer to form a via opening.
10. The method of claim 9 , wherein etching the second dielectric layer comprises:
selectively etching the second dielectric layer with respect to the dielectric capping layer.
11. The method of claim 9 , further comprising:
selectively etching the metal capping layer with respect to the dielectric capping layer.
12. The method of claim 9 , further comprising depositing a liner into the via opening.
13. The method of claim 12 , wherein the liner comprises Co.
14. The method of claim 12 , wherein the liner comprises Ru.
15. The method of claim 12 , wherein the liner comprises Mn.
16. The method of claim 12 , further comprising:
etching the liner from a bottom of the via opening.
17. A method comprising:
selectively depositing a metal capping layer over a metal line disposed in a first dielectric layer;
forming a dielectric capping layer on the metal capping layer and the first dielectric layer, at least a first portion of the dielectric capping layer being non-overlapping with the metal capping layer;
polishing the dielectric capping layer to expose the metal capping layer such that a top surface of an exposed portion of the metal capping layer is substantially co-planar with a top surface the dielectric capping layer;
depositing a second dielectric layer on the top surface of the exposed portion of the metal capping layer;
etching the second dielectric layer to form a via opening; and
selectively etching the metal capping layer with respect to the dielectric capping layer.
18. The method of claim 17 , further comprising depositing a liner into the via opening.
19. The method of claim 18 further comprising:
etching the liner from a bottom of the via opening.