Analog hardware realization of trained neural networks
Systems and methods are provided for analog hardware realization of neural networks. The method incudes obtaining a neural network topology and weights of a trained neural network. The method also includes calculating one or more connection constraints based on analog integrated circuit (IC) design constraints. The method also includes transforming the neural network topology to an equivalent sparsely connected network of analog components satisfying the one or more connection constraints. The method also includes computing a weight matrix for the equivalent sparsely connected network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection between analog components of the equivalent sparsely connected network.
1 . A method for hardware realization of neural networks, comprising:
obtaining a neural network topology and weights of a trained neural network, wherein the neural network topology includes at least one densely connected layer with K inputs, an input connection degree of N i , L outputs, an output connection degree of N o , and a weight matrix U;
calculating one or more connection constraints based on analog integrated circuit (IC) design constraints;
transforming the neural network topology to an equivalent sparsely connected network of analog components satisfying the one or more connection constraints, including transforming the at least one densely connected layer of the trained neural network into a sparsely connected set of M layers in the equivalent sparsely connected network by:
deriving an input connection degree N′ i <N i and output connection degree N′ o <N o , according to the one or more connection constraints;
constructing the set of M layers having K′<K inputs, L′<L outputs, and M≥2 layers so that an input connection degree for the M layers does not exceed Ni, and an output connection degree for the M layers does not exceed N′ o ; and
selecting a plurality of individual electronic analog components for the equivalent sparsely connected network;
computing a weight matrix for the equivalent sparsely connected network based on the weights of the trained neural network, wherein each element of the weight matrix represents a respective connection between a respective pair of individual electronic analog components of the equivalent sparsely connected network; and
generating a schematic model for implementing the equivalent sparsely connected network as electronic circuitry based on the weight matrix, including selecting component values for each individual electronic analog component, wherein:
an electronic circuit implementing the equivalent sparsely connected network has a lower power consumption during use compared to an electronic circuit implementing the trained neural network, fewer analog components than the electronic circuit implementing the trained neural network, and/or a smaller footprint than the electronic circuit implementing the trained neural network.
2 . The method of claim 1 , wherein the at least one densely connected layer is a convolutional layer.
3 . The method of claim 1 , wherein:
the neural network topology includes a recurrent neural layer; and
transforming the neural network topology to the equivalent sparsely connected network of analog components includes transforming the recurrent neural layer into one or more densely or sparsely connected layers with signal delay connections.
4 . The method of claim 1 , wherein the neural network topology includes a single layer perceptron with a calculation neuron with an activation function.
5 . The method of claim 1 , wherein the neural network topology includes a multi-layer perceptron with S layers, each layer i of the S layers includes a corresponding set of calculation neurons L i and corresponding weight matrices that includes a row of weights for each calculation neuron of the L i calculation neurons.
6 . The method of claim 1 , wherein the neural network topology includes a Convolutional Neural Network (CNN) with K inputs, Slayers, each layer i of the S layers includes a corresponding set of calculation neurons Li and corresponding weight matrices Vi that includes a row of weights for each calculation neuron of the Li calculation neurons.
7 . The method of claim 1 , wherein transforming the neural network topology to the equivalent sparsely connected network of analog components comprises performing a trapezium transformation.
8 . The method of claim 7 , wherein the neural network topology includes a multilayer perceptron network, the method further comprising:
for each pair of consecutive layers of the multilayer perceptron network, iteratively performing the trapezium transformation and computing the weight matrix for the equivalent sparsely connected network.
9 . The method of claim 7 , wherein the neural network topology includes a recurrent neural network (RNN) that includes (i) a calculation of a linear combination for two fully connected layers, (ii) an element-wise addition, and (iii) a non-linear function calculation, the method further comprising:
performing the trapezium transformation and computing the weight matrix for the equivalent sparsely connected network for (i) the two fully connected layers and (ii) the non-linear function calculation.
10 . The method of claim 7 , wherein the neural network topology includes a long short-term memory (LSTM) network or a gated recurrent unit (GRU) network that includes (i) a calculation of a linear combination for a plurality of fully connected layers, (ii) an element-wise addition, (iii) a Hadamard product, and (iv) a plurality of non-linear function calculations, the method further comprising:
performing the trapezium transformation and computing the weight matrix for the equivalent sparsely connected network for (i) the plurality of fully connected layers and (ii) the plurality of non-linear function calculations.
11 . The method of claim 7 , wherein the neural network topology includes a convolutional neural network (CNN) that includes (i) a plurality of partially connected layers and (ii) one or more fully-connected layers, the method further comprising:
transforming the plurality of partially connected layers into equivalent fully-connected layers by inserting missing connections with zero weights; and
for each pair of consecutive layers of the equivalent fully-connected layers and the one or more fully-connected layers, iteratively performing the trapezium transformation and computing the weight matrix for the equivalent sparsely connected network.
12 . The method of claim 1 , wherein:
each output neuron performs an activation function F;
transforming the neural network topology to the equivalent sparsely connected network of analog components comprises performing an approximation transformation that comprises:
constructing a pyramid neural network that forms first p layers of the equivalent sparsely connected network, wherein each neuron in the pyramid neural network performs identity function; and
constructing a trapezium neural network, wherein each neuron in last layer of the trapezium neural network performs the activation function F and all other neurons perform identity function, and
computing the weight matrix for the equivalent sparsely connected network comprises:
generating weights for the pyramid neural network; and
generating weights for the trapezium neural network.
13 . The method of claim 12 , wherein:
the neural network topology includes a multilayer perceptron with S layers; and
transforming the neural network topology to the equivalent sparsely connected network of analog components comprises:
for each layer j of the S layers of the multilayer perceptron:
constructing a respective pyramid-trapezium network PTNNX j by performing the approximation transformation to a respective single layer perceptron; and
constructing the equivalent sparsely connected network by stacking each pyramid trapezium network so that an output of a pyramid trapezium network PTNNXj−1 is set as an input for pyramid trapezium network PTNNXj.
14 . A system for hardware realization of neural networks, comprising:
one or more processors;
memory;
wherein the memory stores one or more programs configured for execution by the one or more processors, and the one or more programs comprise instructions for:
obtaining a neural network topology and weights of a trained neural network, wherein the neural network topology includes at least one densely connected layer with K inputs, an input connection degree of N i , L outputs, an output connection degree of N o , and a weight matrix U;
calculating one or more connection constraints based on analog integrated circuit (IC) design constraints;
transforming the neural network topology to an equivalent sparsely connected network of analog components satisfying the one or more connection constraints, including transforming the at least one densely connected layer of the trained neural network into a sparsely connected set of M layers in the equivalent sparsely connected network by:
deriving an input connection degree N′ i <N i and an output connection degree N′ o <N o , according to the one or more connection constraints;
constructing the set of M layers having K′<K inputs, L′<L outputs, and M≥2 layers so that an input connection degree for the M layers does not exceed Ni, and an output connection degree for the M layers does not exceed N′ o ; and
selecting a plurality of individual electronic analog components for the equivalent sparsely connected network;
computing a weight matrix for the equivalent sparsely connected network based on the weights of the trained neural network, wherein each element of the weight matrix represents a respective connection between a respective pair of individual electronic analog components of the equivalent sparsely connected network; and
generating a schematic model for implementing the equivalent sparsely connected network as electronic circuitry based on the weight matrix, including selecting component values for each individual electronic analog component, wherein:
an electronic circuit implementing the equivalent sparsely connected network has a lower power consumption during use compared to an electronic circuit implementing the trained neural network, fewer analog components than the electronic circuit implementing the trained neural network, and/or a smaller footprint than the electronic circuit implementing the trained neural network.
15 . A non-transitory computer readable storage medium storing one or more programs configured for execution by a computer system having one or more processors, the one or more programs comprising instructions for:
obtaining a neural network topology and weights of a trained neural network, wherein the neural network topology includes a single sparsely connected layer with K inputs, an input connection degree of N i , L outputs, an output connection degree of N o , and a weight matrix U, where absent connections are represented with zeros;
calculating one or more connection constraints based on analog integrated circuit (IC) design constraints;
transforming the neural network topology to an equivalent sparsely connected network of analog components satisfying the one or more connection constraints, including transforming the at least one densely connected layer of the trained neural network into a sparsely connected set of M layers in the equivalent sparsely connected network by:
deriving an input connection degree N′ i <N i and an output connection degree N′ o <N o , according to the one or more connection constraints;
constructing the set of M layers having K′<K inputs, L′<L outputs, and M≥2 layers so that an input connection degree for the M layers does not exceed N′ i , and an output connection degree for the M layers does not exceed N′ o ; and
selecting a plurality of individual electronic analog components for the equivalent sparsely connected network;
computing a weight matrix for the equivalent sparsely connected network based on the weights of the trained neural network, wherein each element of the weight matrix represents a respective connection between a respective pair of individual electronic analog components of the equivalent sparsely connected network; and
generating a schematic model for implementing the equivalent sparsely connected network as electronic circuitry based on the weight matrix, including selecting component values for each individual electronic analog component, wherein:
an electronic circuit implementing the equivalent sparsely connected network has a lower power consumption during use compared to an electronic circuit implementing the trained neural network, fewer analog components than the electronic circuit implementing the trained neural network, and/or a smaller footprint than the electronic circuit implementing the trained neural network.