Granted Patent B2

US 12,632,716 · App. 17/029,579 · Granted May 19, 2026

Inventor: Win-San Khwa (Hsinchu, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

G06N3/065G06N3/04G06N3/082

Abstract

Claims (90)

1 . A system, comprising:

at least one processor configured to establish a neural network that comprises a first layer and a second layer;

a memory device coupled to the at least one processor and configured to store a plurality of weight values that are associated with the first layer and the second layer in the neural network, wherein a memory cell of the memory device comprises:

a resistor; and

a first transistor, wherein a gate terminal of the first transistor is coupled to a word line;

a dropout device coupled to the memory device,

wherein the dropout device is configured to deny an assessment to at least one of the plurality of weight values stored in the memory device, in response to a dropout control signal, and the second layer of the neural network being computed regardless of the at least one of the plurality of weight values that is not accessed, wherein the dropout device comprises:

a second transistor,

wherein the gate terminal of the first transistor is configured to receive an input signal, and a gate terminal of the second transistor is configured to receive the dropout control signal; and

a comparator device,

wherein a first terminal of the first transistor is coupled to the resistor, and a second terminal of the first transistor is coupled to the comparator device,

wherein the input signal is transmitted through the word line to the gate terminal of the first transistor and a drain terminal of the second transistor.

2 . The system of claim 1 , wherein the resistor is configured to store one of the plurality of weight values,

wherein the drain terminal of the second transistor is coupled through the word line to the gate terminal of the first transistor.

3 . The system of claim 2 , wherein

a source terminal of the second transistor is coupled to a first reference terminal,

the second transistor is configured to pull low the input signal transmitted through the word line to the first reference terminal or to bypass the gate terminal of the first transistor, in response to the dropout control signal, and

the input signal is generated by the at least one processor according to data from a first neural node in the first layer.

4 . The system of claim 3 , wherein the second terminal of the first transistor is configured to generate an output signal as a second neural node of the second layer, according to the at least one of the plurality of weight values that is not accessed and the input signal.

5 . The system of claim 1 , wherein the comparator device is coupled with the memory device,

wherein the comparator device is configured to compare an output signal generated by the first transistor of the memory device with a reference signal and to generate digital data, and the digital data is collected by the at least one processor into a second neural node in the second layer.

6 . The system of claim 1 , wherein

in response to the dropout control signal with a first logic level, the dropout device is configured to pull low the input signal generated from the first layer, wherein the pulled low input signal denies the assessment to a first weight value of the plurality of weight values, and

in response to the dropout control signal with a second logic level, the dropout device is configured to bypass the input signal generated from the first layer to the memory cell of the memory device, for activating the memory cell storing the first weight value, wherein an output signal is generated in reference with the input signal and the first weight value and collected into a second neural node in the second layer.

7 . The system of claim 1 , wherein when the second transistor is turned off by the dropout control signal, the second transistor bypasses the input signal different from the dropout control signal to the gate terminal of the first transistor,

wherein when the second transistor is turned on by the dropout control signal, the second transistor bypasses the input signal different from the dropout control signal to a ground.

8 . A system, comprising:

at least one memory device configured to store a neural network and a plurality of weight values that are associated with the neural network, the neural network comprising a first layer and a second layer;

a dropout device coupled to the at least one memory device, wherein the system is executed by at least one processor to operate:

generating an input signal according to data of a first neural node in the first layer;

pulling low the input signal or bypassing the input signal to the at least one memory device, in response to a dropout control signal received by the dropout device;

denying an assessment to a first weight value of the plurality of weight values stored in the memory device, in response to the pulled low input signal; and

generating an output signal to a second neural node in the second layer, according to the bypassed input signal,

wherein the first weight value is associated with the first neural node in the first layer and the second neural node in the second layer,

wherein a memory cell of the at least one memory device comprises a resistor and a first transistor, and a gate terminal of the first transistor is coupled to a word line,

wherein the dropout device comprises a second transistor,

wherein the gate terminal of the first transistor is configured to receive the input signal, and a gate terminal of the second transistor is configured to receive the dropout control signal; and

a comparator device,

wherein a first terminal of the first transistor is coupled to the resistor, and a second terminal of the first transistor is coupled to the comparator device,

wherein the input signal is transmitted through the word line to the gate terminal of the first transistor and a drain terminal of the second transistor.

9 . The system of claim 8 , wherein

a first terminal of the dropout device is coupled through the word line to the memory cell of the at least one memory device, and a second terminal of the dropout device is coupled to a first reference terminal, and

the system is executed by the at least one processor to operate:

activating the dropout device, in response to the dropout control signal with a first logic level; and

transmitting the input signal from the word line through the activated dropout device to the first reference terminal.

10 . The system of claim 9 , wherein the system is executed by the at least one processor to operate:

deactivating the dropout device, in response to the dropout control signal with a second logic level different from the first logic level; and

transmitting the input signal from the word line through the first terminal of the deactivated dropout device to the at least one memory device.

11 . The system of claim 8 , wherein

the resistor of the memory cell is configured to store the first weight value,

the gate terminal of the first transistor is coupled through the word line to the first neural node and the dropout device,

the first terminal of the first transistor is coupled to a second reference terminal through the resistor, and

the second terminal of the first transistor is coupled to through a modulate line to the second neural node.

12 . The system of claim 11 , wherein the system is executed by the at least one processor to operate:

turning on the first transistor, for accessing the first weight value, when the input signal is bypassed to the gate terminal of the first transistor; or

turning off the first transistor for not accessing the first weight value, when the input signal is pulled low to a first reference terminal,

wherein the output signal is generated from the second terminal of the first transistor and is transmitted through the modulate line to be collected by the at least one processor.

13 . The system of claim 11 , wherein

the second transistor is coupled to the word line,

the gate terminal of the second transistor is configured to receive the dropout control signal,

the drain terminal of the second transistor is coupled to the word line and the gate terminal of the first transistor, and

a source terminal of the second transistor is coupled to a first reference terminal.

14 . The system of claim 8 , wherein

the at least one memory device comprises a plurality of memory cells, wherein each of the plurality of memory cells is coupled to one of word lines and one of modulating lines, and is configured to store one of the plurality of weight values correspondingly,

the input signal is transmitted through the one of the word lines to the dropout device and a part of the plurality of memory cells that are coupled with the one of the word lines, and

the denying the assessment to the first weight value stored in the memory device further comprises:

turning off at least one of the plurality of memory cells that is coupled with the one of the word lines; and

bypassing the input signal from the one of the word lines to the one of the modulating lines that is coupled to the turned off at least one of the plurality of memory cells.

15 . The system of claim 8 , wherein the comparator device is coupled between the at least one memory device and a second reference terminal,

wherein the at least one memory device comprises a switch that is coupled to the dropout device, and the comparator device compares a voltage level of the output signal with a voltage on the second reference terminal to generate digital data, wherein the digital data is collected into a second neural node in the second layer.

16 . The system of claim 8 , wherein when the second transistor is turned off by the dropout control signal, the second transistor bypasses the input signal different from the dropout control signal to the gate terminal of the first transistor,

wherein when the second transistor is turned on by the dropout control signal, the second transistor bypasses the input signal different from the dropout control signal to a ground.

17 . A method, comprising:

receiving input signals generated from a first layer that is included in a neural network, by a dropout device;

determining at least one first neural node of the first layer to be dropped, by the dropout device;

transferring at least one of the input signals that is output from the at least one first neural node to a reference terminal, by the dropout device, in response to a dropout control signal;

denying an assessment to a part of weight values stored in a memory device, wherein the weight values are associated with the at least one first neural node and at least one second neural node of a second layer that is included in the neural network; and

computing data of the second layer of the neural network, according to data of the first layer and the weight values,

wherein a gate terminal of a first transistor of a memory cell of the memory device is coupled to a word line,

wherein the gate terminal of the first transistor is configured to receive the at least one of the input signals, and a gate terminal of a second transistor of the dropout device is configured to receive the dropout control signal,

wherein a first terminal of the first transistor is coupled to a resistor of the memory cell, and a second terminal of the first transistor is coupled to a comparator device of the memory device,

wherein the at least one of the input signals is transmitted through the word line to the gate terminal of the first transistor and a drain terminal of the second transistor.

18 . The method of claim 17 , further comprising:

bypassing the input signals, excluding the at least one of the input signals that is transferred to the reference terminal, to the memory device, in response to the dropout control signal;

activating the memory device for accessing the weight values excluding the part of the weight values that is associated with the at least one first neural node and the at least one second neural node; and

generating output signals to the second layer, according to the bypassed input signals.

19 . The method of claim 18 , further comprising:

modulating the output signals to be operated in a digital domain according to the input signals, by the comparator device coupled to a plurality of transistors that are included in the memory device and are operated to be logic levels.

20 . The method of claim 17 , wherein when the second transistor is turned off by the dropout control signal, the second transistor bypasses the at least one of input signals different from the dropout control signal to the gate terminal of the first transistor,

wherein when the second transistor is turned on by the dropout control signal, the second transistor bypasses the at least one of input signals different from the dropout control signal to the reference terminal.

Assignments (1)

Continuity (2)

References Cited (29)