Granted Patent B2

US 12,353,503 · App. 16/449,205 · Granted Jul 8, 2025

Inventors: Hieu Van Tran (San Jose, CA); Stephen Trinh (San Jose, CA); Thuan Vu (San Jose, CA); Stanley Hong (San Jose, CA); Vipin Tiwari (Dublin, CA); Mark Reiten (Alamo, CA); Nhan Do (Saratoga, CA)

Assignee: Silicon Storage Technology, Inc.

G06F17/16G06N3/065G11C11/54G11C16/0483G11C16/08G11C2216/04

Abstract

Claims (21)

1. A method, comprising:

measuring leakage current from one or more decoding circuits and one or more column write circuits for use with a non-volatile memory array and storing a measured leakage current value in a register;

retrieving the leakage current value from the register; and

converting a neuron output from the non-volatile memory array into a digital value and subtracting the leakage current value from the digital value.

2. A method comprising:

measuring leakage current from one or more decoding circuits and one or more write circuits for use with an array of analog neural memory cells using an analog-to-digital converter to generate a digital leakage current value;

storing the digital leakage current value as a first value in a counter; and

generating an output from a neuron output from the array using the counter and the first value, wherein the output is equal to the neuron output minus the first value.

3. The method in claim 2 , wherein the generating comprises converting a current from the array of analog neural memory cells into the output by counting down on the counter from the stored first value until the counter reaches zero and then counting up to generate the output.

4. The method in claim 2 , wherein the generating comprises measuring a current from the array of analog neural memory cells using the counter and then subtracting the stored first value from the measured current to generate the output.

5. The method of claim 2 , wherein the analog-to-digital converter comprises an integrating analog-to-digital converter.

6. The method of claim 2 , wherein the analog-to-digital converter comprises a ramp analog-to-digital converter.

7. The method of claim 2 , wherein the analog-to-digital converter comprises an algorithmic analog-to-digital converter.

8. The method of claim 2 , wherein the analog-to-digital converter comprises a sigma delta analog-to-digital converter.

9. The method of claim 2 , wherein the analog-to-digital converter comprises a successive approximation register analog-to-digital converter.

10. The method of claim 2 , further comprising:

converting the output into a voltage.

11. The method of claim 2 , further comprising:

converting the output into one or more pulses where the width of the one or more pulses is proportional to the value of the output.

12. The method of claim 2 , wherein the analog neural memory cells are split-gate flash memory cells.

13. The method of claim 2 , wherein the analog neural memory cells are stacked-gate flash memory cells.

Assignments (13)

Continuity (2)

References Cited (108)